Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418679468	2779444	0	0
DepthKnown_A	418679468	417852767	0	0
RvalidKnown_A	418679468	417852767	0	0
WreadyKnown_A	418679468	417852767	0	0
gen_passthru_fifo.paramCheckPass	1195	1195	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	2779444	0	0
T1	48418	14481	0	0
T2	49245	14381	0	0
T3	3763	0	0	0
T4	423289	4992	0	0
T5	48241	13781	0	0
T6	375012	7551	0	0
T14	1964	49	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	12506	0	0
T20	0	61	0	0
T32	0	146	0	0
T42	0	1288	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195	1195	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418679468	3929193	0	0
DepthKnown_A	418679468	417852767	0	0
RvalidKnown_A	418679468	417852767	0	0
WreadyKnown_A	418679468	417852767	0	0
gen_passthru_fifo.paramCheckPass	1195	1195	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	3929193	0	0
T1	48418	5775	0	0
T2	49245	6111	0	0
T3	3763	0	0	0
T4	423289	22337	0	0
T5	48241	5896	0	0
T6	375012	7551	0	0
T14	1964	49	0	0
T15	2205	0	0	0
T16	1578	0	0	0
T17	1835	0	0	0
T18	0	4749	0	0
T20	0	61	0	0
T32	0	146	0	0
T42	0	5591	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195	1195	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418679468	24378221	0	0
DepthKnown_A	418679468	417852767	0	0
RvalidKnown_A	418679468	417852767	0	0
WreadyKnown_A	418679468	417852767	0	0
gen_passthru_fifo.paramCheckPass	1195	1195	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	24378221	0	0
T1	48418	13078	0	0
T2	49245	13717	0	0
T3	3763	506	0	0
T4	423289	30229	0	0
T5	48241	13324	0	0
T6	375012	37268	0	0
T14	1964	535	0	0
T15	2205	152	0	0
T16	1578	107	0	0
T17	1835	108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195	1195	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	418679468	31738032	0	0
DepthKnown_A	418679468	417852767	0	0
RvalidKnown_A	418679468	417852767	0	0
WreadyKnown_A	418679468	417852767	0	0
gen_passthru_fifo.paramCheckPass	1195	1195	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	31738032	0	0
T1	48418	13078	0	0
T2	49245	13717	0	0
T3	3763	506	0	0
T4	423289	136004	0	0
T5	48241	13324	0	0
T6	375012	37268	0	0
T14	1964	535	0	0
T15	2205	152	0	0
T16	1578	107	0	0
T17	1835	107	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	418679468	417852767	0	0
T1	48418	48324	0	0
T2	49245	49177	0	0
T3	3763	3090	0	0
T4	423289	407288	0	0
T5	48241	48180	0	0
T6	375012	374914	0	0
T14	1964	1814	0	0
T15	2205	2125	0	0
T16	1578	1411	0	0
T17	1835	1655	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1195	1195	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0