Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21623553	1		T1	24961		T2	196		T3	503
full_word	6348725	1		T1	18636		T2	47		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	27971978	1		T1	43597		T2	243		T3	505
auto[TlIntgErrCmd]	101	1		T60	10		T226	7		T243	2
auto[TlIntgErrData]	103	1		T60	5		T226	8		T243	5
auto[TlIntgErrBoth]	96	1		T60	5		T226	5		T243	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24150888	1		T1	29671		T2	191		T3	497
auto[1]	3821390	1		T1	13926		T2	52		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21140580	1		T1	23125		T2	188		T3	496
auto[TlIntgErrNone]	partial	auto[1]	482707	1		T1	1836		T2	8		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	3010174	1		T1	6546		T2	3		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3338517	1		T1	12090		T2	44		T3	1
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T60	4		T226	4		T243	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T60	5		T226	3		T239	4
auto[TlIntgErrCmd]	full_word	auto[0]	11	1		T60	1		T243	1		T239	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T239	1		T278	1		T271	2
auto[TlIntgErrData]	partial	auto[0]	44	1		T60	1		T226	5		T243	1
auto[TlIntgErrData]	partial	auto[1]	48	1		T60	3		T226	2		T243	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T60	1		T278	1		T358	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T226	1		T243	1		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T60	2		T226	1		T239	2
auto[TlIntgErrBoth]	partial	auto[1]	53	1		T60	2		T226	4		T243	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T60	1		T239	1		T359	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T271	1		T309	1		T274	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	21261	1		T58	55		T60	15		T173	1505
full_word	2652451	1		T4	16420		T5	41474		T18	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2673434	1		T4	16420		T5	41474		T18	9
auto[TlIntgErrCmd]	78	1		T60	6		T226	5		T243	4
auto[TlIntgErrData]	95	1		T60	5		T226	7		T243	1
auto[TlIntgErrBoth]	105	1		T60	6		T226	6		T243	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2646049	1		T4	16420		T5	41474		T18	9
auto[1]	27663	1		T58	56		T60	11		T173	1930

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1321	1		T58	5		T173	118		T174	8
auto[TlIntgErrNone]	partial	auto[1]	19689	1		T58	50		T173	1387		T174	48
auto[TlIntgErrNone]	full_word	auto[0]	2644611	1		T4	16420		T5	41474		T18	9
auto[TlIntgErrNone]	full_word	auto[1]	7813	1		T58	6		T173	543		T174	73
auto[TlIntgErrCmd]	partial	auto[0]	23	1		T60	3		T239	1		T244	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T60	2		T226	5		T243	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T278	1		T360	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T60	1		T244	1		T271	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T60	2		T226	6		T239	2
auto[TlIntgErrData]	partial	auto[1]	40	1		T60	3		T226	1		T243	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T357	2		T360	1		T361	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T271	1		T362	1		T309	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T60	1		T226	2		T243	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T60	4		T226	4		T243	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T239	1		T271	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T60	1		T362	2		T363	1