Unified Coverage Report :: Module :: flash_phy_rd_buf_dep

Module : flash_phy_rd_buf_dep

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep	96.59	100.00	86.36			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.59	100.00	86.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.44	100.00	89.77			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Module : flash_phy_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T4,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Branch Coverage for Module : flash_phy_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	825775258	4614039	0	0
BufferDepRsp_A	825775258	824083018	0	0
BufferIncrOverFlow_A	825775258	4614055	0	0
DepBufferRspOrder_A	825775261	14364792	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825775258	4614039	0	0
T1	489410	5808	0	0
T2	885	0	0	0
T3	3936	0	0	0
T4	1636668	29028	0	0
T5	693170	45836	0	0
T6	5739	228	0	0
T10	130627	0	0	0
T11	827118	0	0	0
T15	4554	0	0	0
T16	730676	753	0	0
T17	3544	0	0	0
T18	5189	112	0	0
T19	0	25261	0	0
T25	128388	1024	0	0
T26	0	1711	0	0
T34	0	512	0	0
T39	0	14	0	0
T40	211262	2680	0	0
T54	0	18	0	0
T55	0	3	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825775258	824083018	0	0
T1	978820	942468	0	0
T2	1770	1596	0	0
T3	7872	6506	0	0
T4	1636668	1636368	0	0
T5	693170	693058	0	0
T10	261254	260964	0	0
T11	827118	827086	0	0
T15	4554	4342	0	0
T16	730676	730480	0	0
T17	3544	3274	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825775258	4614055	0	0
T1	489410	5808	0	0
T2	885	0	0	0
T3	3936	0	0	0
T4	1636668	29028	0	0
T5	693170	45836	0	0
T6	5739	228	0	0
T10	130627	0	0	0
T11	827118	0	0	0
T15	4554	0	0	0
T16	730676	753	0	0
T17	3544	0	0	0
T18	5189	112	0	0
T19	0	25261	0	0
T25	128388	1024	0	0
T26	0	1711	0	0
T34	0	512	0	0
T39	0	14	0	0
T40	211262	2680	0	0
T54	0	18	0	0
T55	0	3	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	825775261	14364792	0	0
T1	489410	13488	0	0
T2	885	32	0	0
T3	3936	208	0	0
T4	1636668	29061	0	0
T5	693170	45868	0	0
T6	5739	128	0	0
T10	130627	32	0	0
T11	827118	263744	0	0
T15	4554	64	0	0
T16	730676	785	0	0
T17	3544	64	0	0
T18	5189	0	0	0
T19	0	25261	0	0
T25	128388	0	0	0
T26	0	612	0	0
T39	0	14	0	0
T40	211262	0	0	0
T54	0	11	0	0
T67	0	131072	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T5
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T56
1	1	Covered	T1,T4,T5

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T56
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T4,T5
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T4,T5
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	412887629	2846510	0	0
BufferDepRsp_A	412887629	412041509	0	0
BufferIncrOverFlow_A	412887629	2846518	0	0
DepBufferRspOrder_A	412887631	8082441	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	2846510	0	0
T1	489410	5808	0	0
T2	885	0	0	0
T3	3936	0	0	0
T4	818334	15649	0	0
T5	346585	23599	0	0
T6	0	100	0	0
T10	130627	0	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	450	0	0
T17	1772	0	0	0
T18	0	112	0	0
T25	0	1024	0	0
T26	0	1099	0	0
T40	0	2680	0	0
T54	0	7	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	2846518	0	0
T1	489410	5808	0	0
T2	885	0	0	0
T3	3936	0	0	0
T4	818334	15649	0	0
T5	346585	23599	0	0
T6	0	100	0	0
T10	130627	0	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	450	0	0
T17	1772	0	0	0
T18	0	112	0	0
T25	0	1024	0	0
T26	0	1099	0	0
T40	0	2680	0	0
T54	0	7	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887631	8082441	0	0
T1	489410	13488	0	0
T2	885	32	0	0
T3	3936	208	0	0
T4	818334	15682	0	0
T5	346585	23631	0	0
T10	130627	32	0	0
T11	413559	132672	0	0
T15	2277	64	0	0
T16	365338	482	0	0
T17	1772	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
TOTAL		23	23	100.00
ALWAYS	48	7	7	100.00
CONT_ASSIGN	61	1	1	100.00
CONT_ASSIGN	62	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00
ALWAYS	76	6	6	100.00
ALWAYS	90	3	3	100.00
CONT_ASSIGN	97	1	1	100.00
ALWAYS	116	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
			MISSING_ELSE
54	1	1
55	1	1
			MISSING_ELSE
61	1	1
62	1	1
65	1	1
66	1	1
71	1	1
72	1	1
76	1	1
77	1	1
79	1	1
80	1	1
			MISSING_ELSE
82	1	1
83	1	1
			MISSING_ELSE
90	1	1
91	1	1
92	1	1
97	1	1
116		unreachable
117		unreachable
118		unreachable

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (en_i & fifo_wr_i & (curr_incr_cnt < flash_phy_pkg::RspOrderDepth))
             --1-   ----2----   -----------------------3----------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T11,T67,T74
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T16

 LINE       66
 EXPRESSION (en_i & fifo_rd_i & (curr_decr_cnt > '0))
             --1-   ----2----   ----------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T16
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T16

 LINE       71
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (cnt_incr && ((!cnt_decr))) : cnt_incr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       71
 SUB-EXPRESSION (cnt_incr && ((!cnt_decr)))
                 ----1---    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T19
1	1	Covered	T4,T5,T16

 LINE       72
 EXPRESSION ((incr_buf_sel == decr_buf_sel) ? (((!cnt_incr)) && cnt_decr) : cnt_decr)
             ---------------1--------------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (incr_buf_sel == decr_buf_sel)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       72
 SUB-EXPRESSION (((!cnt_incr)) && cnt_decr)
                 ------1------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Line No.	Total	Covered	Percent
Branches		13	13	100.00
TERNARY	71	2	2	100.00
TERNARY	72	2	2	100.00
IF	51	2	2	100.00
IF	54	2	2	100.00
IF	76	5	5	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buf_dep.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

	LineNo.	Expression
-1-:	72	((incr_buf_sel == decr_buf_sel)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

	LineNo.	Expression
-1-:	51	if (wr_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	54	if (rd_buf_i[i])

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	79	if (fin_cnt_incr)
-3-:	82	if (fin_cnt_decr)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T16
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T4,T5,T16
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BufferDecrUnderRun_A	412887629	1767529	0	0
BufferDepRsp_A	412887629	412041509	0	0
BufferIncrOverFlow_A	412887629	1767537	0	0
DepBufferRspOrder_A	412887630	6282351	0	0

BufferDecrUnderRun_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	1767529	0	0
T4	818334	13379	0	0
T5	346585	22237	0	0
T6	5739	128	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	303	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	25261	0	0
T25	128388	0	0	0
T26	0	612	0	0
T34	0	512	0	0
T39	0	14	0	0
T40	211262	0	0	0
T54	0	11	0	0
T55	0	3	0	0

BufferDepRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

BufferIncrOverFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	1767537	0	0
T4	818334	13379	0	0
T5	346585	22237	0	0
T6	5739	128	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	303	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	25261	0	0
T25	128388	0	0	0
T26	0	612	0	0
T34	0	512	0	0
T39	0	14	0	0
T40	211262	0	0	0
T54	0	11	0	0
T55	0	3	0	0

DepBufferRspOrder_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887630	6282351	0	0
T4	818334	13379	0	0
T5	346585	22237	0	0
T6	5739	128	0	0
T11	413559	131072	0	0
T15	2277	0	0	0
T16	365338	303	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	25261	0	0
T25	128388	0	0	0
T26	0	612	0	0
T39	0	14	0	0
T40	211262	0	0	0
T54	0	11	0	0
T67	0	131072	0	0