Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1651550516	1648166036	0	0
CheckNGreaterZero_A	3924	3924	0	0
GntImpliesReady_A	1651550516	438587561	0	0
GntImpliesValid_A	1651550516	438587561	0	0
GrantKnown_A	1651550516	1648166036	0	0
IdxKnown_A	1651550516	1648166036	0	0
IndexIsCorrect_A	1651550516	438587561	0	0
NoReadyValidNoGrant_A	1651550516	166302058	0	0
Priority_A	1651550516	460663929	0	0
ReadyAndValidImplyGrant_A	1651550516	438587561	0	0
ReqAndReadyImplyGrant_A	1651550516	438587561	0	0
ReqImpliesValid_A	1651550516	460663929	0	0
ValidKnown_A	1651550516	1648166036	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	1648166036	0	0
T1	1957640	1884936	0	0
T2	3540	3192	0	0
T3	15744	13012	0	0
T4	3273336	3272736	0	0
T5	1386340	1386116	0	0
T10	522508	521928	0	0
T11	1654236	1654172	0	0
T15	9108	8684	0	0
T16	1461352	1460960	0	0
T17	7088	6548	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3924	3924	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	438587561	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	58122	0	0
T5	1386340	451340	0	0
T6	11478	2440	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	174482	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	438587561	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	58122	0	0
T5	1386340	451340	0	0
T6	11478	2440	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	174482	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	1648166036	0	0
T1	1957640	1884936	0	0
T2	3540	3192	0	0
T3	15744	13012	0	0
T4	3273336	3272736	0	0
T5	1386340	1386116	0	0
T10	522508	521928	0	0
T11	1654236	1654172	0	0
T15	9108	8684	0	0
T16	1461352	1460960	0	0
T17	7088	6548	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	1648166036	0	0
T1	1957640	1884936	0	0
T2	3540	3192	0	0
T3	15744	13012	0	0
T4	3273336	3272736	0	0
T5	1386340	1386116	0	0
T10	522508	521928	0	0
T11	1654236	1654172	0	0
T15	9108	8684	0	0
T16	1461352	1460960	0	0
T17	7088	6548	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	438587561	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	58122	0	0
T5	1386340	451340	0	0
T6	11478	2440	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	174482	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	166302058	0	0
T1	978820	89592	0	0
T2	1770	256	0	0
T3	7872	1664	0	0
T4	3273336	1861078	0	0
T5	1386340	187164	0	0
T6	11478	394	0	0
T10	261254	256	0	0
T11	1654236	2109952	0	0
T15	9108	512	0	0
T16	1461352	2578	0	0
T17	7088	512	0	0
T18	10378	0	0	0
T19	0	112094	0	0
T25	256776	0	0	0
T26	0	1850	0	0
T39	0	56	0	0
T40	422524	0	0	0
T54	0	34	0	0
T67	0	1048576	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	460663929	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	593586	0	0
T5	1386340	567870	0	0
T6	11478	2506	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	226830	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	438587561	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	58122	0	0
T5	1386340	451340	0	0
T6	11478	2440	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	174482	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	438587561	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	58122	0	0
T5	1386340	451340	0	0
T6	11478	2440	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	174482	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	460663929	0	0
T1	978820	314982	0	0
T2	1770	584	0	0
T3	7872	440	0	0
T4	3273336	593586	0	0
T5	1386340	567870	0	0
T6	11478	2506	0	0
T10	261254	734	0	0
T11	1654236	514650	0	0
T15	9108	262	0	0
T16	1461352	711912	0	0
T17	7088	148	0	0
T18	10378	0	0	0
T19	0	226830	0	0
T25	256776	0	0	0
T26	0	1082250	0	0
T39	0	18032	0	0
T40	422524	0	0	0
T54	0	424	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651550516	1648166036	0	0
T1	1957640	1884936	0	0
T2	3540	3192	0	0
T3	15744	13012	0	0
T4	3273336	3272736	0	0
T5	1386340	1386116	0	0
T10	522508	521928	0	0
T11	1654236	1654172	0	0
T15	9108	8684	0	0
T16	1461352	1460960	0	0
T17	7088	6548	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412887629	412041509	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	412887629	121564839	0	0
GntImpliesValid_A	412887629	121564839	0	0
GrantKnown_A	412887629	412041509	0	0
IdxKnown_A	412887629	412041509	0	0
IndexIsCorrect_A	412887629	121564839	0	0
NoReadyValidNoGrant_A	412887629	43797669	0	0
Priority_A	412887629	127253359	0	0
ReadyAndValidImplyGrant_A	412887629	121564839	0	0
ReqAndReadyImplyGrant_A	412887629	121564839	0	0
ReqImpliesValid_A	412887629	127253359	0	0
ValidKnown_A	412887629	412041509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121564839	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121564839	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121564839	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	43797669	0	0
T1	489410	44796	0	0
T2	885	128	0	0
T3	3936	832	0	0
T4	818334	496364	0	0
T5	346585	50683	0	0
T10	130627	128	0	0
T11	413559	530688	0	0
T15	2277	256	0	0
T16	365338	823	0	0
T17	1772	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	127253359	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	160368	0	0
T5	346585	180153	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121564839	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121564839	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	127253359	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	160368	0	0
T5	346585	180153	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412887629	412041509	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	412887629	121409712	0	0
GntImpliesValid_A	412887629	121409712	0	0
GrantKnown_A	412887629	412041509	0	0
IdxKnown_A	412887629	412041509	0	0
IndexIsCorrect_A	412887629	121409712	0	0
NoReadyValidNoGrant_A	412887629	43797671	0	0
Priority_A	412887629	127098230	0	0
ReadyAndValidImplyGrant_A	412887629	121409712	0	0
ReqAndReadyImplyGrant_A	412887629	121409712	0	0
ReqImpliesValid_A	412887629	127098230	0	0
ValidKnown_A	412887629	412041509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121409712	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121409712	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121409712	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	43797671	0	0
T1	489410	44796	0	0
T2	885	128	0	0
T3	3936	832	0	0
T4	818334	496364	0	0
T5	346585	50683	0	0
T10	130627	128	0	0
T11	413559	530688	0	0
T15	2277	256	0	0
T16	365338	823	0	0
T17	1772	256	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	127098230	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	160368	0	0
T5	346585	180153	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121409712	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	121409712	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	15682	0	0
T5	346585	146460	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	127098230	0	0
T1	489410	157491	0	0
T2	885	292	0	0
T3	3936	220	0	0
T4	818334	160368	0	0
T5	346585	180153	0	0
T10	130627	367	0	0
T11	413559	129428	0	0
T15	2277	131	0	0
T16	365338	345860	0	0
T17	1772	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T16
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412887629	412041509	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	412887629	97806505	0	0
GntImpliesValid_A	412887629	97806505	0	0
GrantKnown_A	412887629	412041509	0	0
IdxKnown_A	412887629	412041509	0	0
IndexIsCorrect_A	412887629	97806505	0	0
NoReadyValidNoGrant_A	412887629	39353359	0	0
Priority_A	412887629	103156170	0	0
ReadyAndValidImplyGrant_A	412887629	97806505	0	0
ReqAndReadyImplyGrant_A	412887629	97806505	0	0
ReqImpliesValid_A	412887629	103156170	0	0
ValidKnown_A	412887629	412041509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	39353359	0	0
T4	818334	434175	0	0
T5	346585	42899	0	0
T6	5739	197	0	0
T11	413559	524288	0	0
T15	2277	0	0	0
T16	365338	466	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	56047	0	0
T25	128388	0	0	0
T26	0	925	0	0
T39	0	28	0	0
T40	211262	0	0	0
T54	0	17	0	0
T67	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	103156170	0	0
T4	818334	136425	0	0
T5	346585	103782	0	0
T6	5739	1253	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	113415	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	103156170	0	0
T4	818334	136425	0	0
T5	346585	103782	0	0
T6	5739	1253	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	113415	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T16
1	0	Covered	T4,T5,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T16
1	1	Covered	T4,T5,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412887629	412041509	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	412887629	97806505	0	0
GntImpliesValid_A	412887629	97806505	0	0
GrantKnown_A	412887629	412041509	0	0
IdxKnown_A	412887629	412041509	0	0
IndexIsCorrect_A	412887629	97806505	0	0
NoReadyValidNoGrant_A	412887629	39353359	0	0
Priority_A	412887629	103156170	0	0
ReadyAndValidImplyGrant_A	412887629	97806505	0	0
ReqAndReadyImplyGrant_A	412887629	97806505	0	0
ReqImpliesValid_A	412887629	103156170	0	0
ValidKnown_A	412887629	412041509	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	39353359	0	0
T4	818334	434175	0	0
T5	346585	42899	0	0
T6	5739	197	0	0
T11	413559	524288	0	0
T15	2277	0	0	0
T16	365338	466	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	56047	0	0
T25	128388	0	0	0
T26	0	925	0	0
T39	0	28	0	0
T40	211262	0	0	0
T54	0	17	0	0
T67	0	524288	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	103156170	0	0
T4	818334	136425	0	0
T5	346585	103782	0	0
T6	5739	1253	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	113415	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	97806505	0	0
T4	818334	13379	0	0
T5	346585	79210	0	0
T6	5739	1220	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	87241	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	103156170	0	0
T4	818334	136425	0	0
T5	346585	103782	0	0
T6	5739	1253	0	0
T11	413559	127897	0	0
T15	2277	0	0	0
T16	365338	10096	0	0
T17	1772	10	0	0
T18	5189	0	0	0
T19	0	113415	0	0
T25	128388	0	0	0
T26	0	541125	0	0
T39	0	9016	0	0
T40	211262	0	0	0
T54	0	212	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0