Module Definition
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Module : prim_fifo_sync_cnt
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.48 98.77 96.67 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt 68.82 90.91 60.00 55.56
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt 79.26 100.00 60.00 77.78
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt 90.30 100.00 80.00 90.91
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt 92.40 92.59 100.00 84.62
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
90.30 100.00
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
79.26 100.00
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
68.82 90.91
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
81.58 92.00
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
81.58 92.00
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11377100.00
ALWAYS12577100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
109 1 1

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
92.40 92.59
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL272592.59
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS1138787.50
ALWAYS1258787.50
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 0 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 0 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2525100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11377100.00
ALWAYS12577100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 unreachable
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 unreachable
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL1212100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
CONT_ASSIGN10911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
109 1 1

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions1313100.00
Logical1313100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T40 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T40 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT12
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT12
1CoveredT1,T2,T3 

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T14
10CoveredT12,T13,T14
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T4
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions1313100.00
Logical1313100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T19 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (2'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T6,T19 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((2'(wptr_o) - 2'(rptr_o))) : (((2'(Depth) - 2'(rptr_o)) + 2'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       109
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T13,T14
10CoveredT12,T13,T14
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
92.40 100.00
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T26,T27 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (5'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((5'(wptr_o) - 5'(rptr_o))) : (((5'(Depth) - 5'(rptr_o)) + 5'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT25,T26,T27 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((5'(wptr_o) - 5'(rptr_o))) : (((5'(Depth) - 5'(rptr_o)) + 5'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
90.30 80.00
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
79.26 60.00
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
68.82 60.00
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
81.58 80.00
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
81.58 80.00
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T25 

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T16,T25 

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT1,T10,T5
1CoveredT1,T2,T3 

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T10,T5
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 + Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 + Depth=16,Secure=0,PtrW=4,DepthW=5,WrapPtrW=5 + Depth=2,Secure=0,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.30 90.91
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
79.26 77.78
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
68.82 55.56
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
81.58 72.73
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
81.58 72.73
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
92.40 84.62
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T4,T5
0 1 Covered T1,T2,T3
0 0 Covered T1,T10,T4 



	LineNo.	Expression
-1-:	113	if ((!rst_ni))
-2-:	115	if (clr_i)
-3-:	117	if (wptr_wrap_set)
-4-:	119	if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T10,T4
0 0 0 1 Covered T1,T10,T4
0 0 0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	125	if ((!rst_ni))
-2-:	127	if (clr_i)
-3-:	129	if (rptr_wrap_set)
-4-:	131	if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T1,T2,T3
0 0 0 1 Covered T1,T2,T10
0 0 0 0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=1,PtrW=1,DepthW=1,WrapPtrW=2 + Depth=2,Secure=1,PtrW=1,DepthW=2,WrapPtrW=2 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCOREBRANCH
100.00 100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
Branches 3 3 100.00
TERNARY 68 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	68	(full_o) ? 
-2-:	68	((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T5,T40
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%