Unified Coverage Report :: Module Instance :: tb.dut.u_tl_adapter_eflash.u_rspfifo

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.98	100.00	83.62			96.30	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.19	100.00	80.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	82.76	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	82.76	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.15	100.00	84.62			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	100.00	83.78	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T19
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T52,T53
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T56,T47,T68
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412887629	3603423	0	0
DepthKnown_A	412887629	412041509	0	0
RvalidKnown_A	412887629	412041509	0	0
WreadyKnown_A	412887629	412041509	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412887629	3603423	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	3603423	0	0
T4	818334	16420	0	0
T5	346585	41474	0	0
T6	5739	161	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	9	0	0
T19	0	41510	0	0
T20	0	8	0	0
T25	128388	0	0	0
T34	0	404	0	0
T40	211262	0	0	0
T55	0	10	0	0
T56	0	381	0	0
T57	0	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	3603423	0	0
T4	818334	16420	0	0
T5	346585	41474	0	0
T6	5739	161	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	9	0	0
T19	0	41510	0	0
T20	0	8	0	0
T25	128388	0	0	0
T34	0	404	0	0
T40	211262	0	0	0
T55	0	10	0	0
T56	0	381	0	0
T57	0	21	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412887629	28493761	0	0
DepthKnown_A	412887629	412041509	0	0
RvalidKnown_A	412887629	412041509	0	0
WreadyKnown_A	412887629	412041509	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412887629	28493761	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	28493761	0	0
T4	818334	588489	0	0
T5	346585	149893	0	0
T6	5739	248	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	36	0	0
T19	0	154673	0	0
T20	0	32	0	0
T25	128388	0	0	0
T34	0	606	0	0
T40	211262	0	0	0
T55	0	18	0	0
T56	0	142	0	0
T57	0	32	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	28493761	0	0
T4	818334	588489	0	0
T5	346585	149893	0	0
T6	5739	248	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	36	0	0
T19	0	154673	0	0
T20	0	32	0	0
T25	128388	0	0	0
T34	0	606	0	0
T40	211262	0	0	0
T55	0	18	0	0
T56	0	142	0	0
T57	0	32	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T5,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412887629	110386420	0	0
DepthKnown_A	412887629	412041509	0	0
RvalidKnown_A	412887629	412041509	0	0
WreadyKnown_A	412887629	412041509	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412887629	110386420	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	110386420	0	0
T1	489410	181550	0	0
T2	885	290	0	0
T3	3936	218	0	0
T4	818334	12588	0	0
T5	346585	183641	0	0
T10	130627	359	0	0
T11	413559	796488	0	0
T15	2277	118	0	0
T16	365338	345415	0	0
T17	1772	64	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	110386420	0	0
T1	489410	181550	0	0
T2	885	290	0	0
T3	3936	218	0	0
T4	818334	12588	0	0
T5	346585	183641	0	0
T10	130627	359	0	0
T11	413559	796488	0	0
T15	2277	118	0	0
T16	365338	345415	0	0
T17	1772	64	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T16,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5,T16,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T16,T11
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412887629	81762891	0	0
DepthKnown_A	412887629	412041509	0	0
RvalidKnown_A	412887629	412041509	0	0
WreadyKnown_A	412887629	412041509	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412887629	81762891	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	81762891	0	0
T4	818334	10953	0	0
T5	346585	104670	0	0
T6	5739	1179	0	0
T11	413559	786944	0	0
T15	2277	0	0	0
T16	365338	9829	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	120093	0	0
T25	128388	0	0	0
T26	0	543229	0	0
T39	0	8839	0	0
T40	211262	0	0	0
T54	0	222	0	0
T67	0	786944	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	81762891	0	0
T4	818334	10953	0	0
T5	346585	104670	0	0
T6	5739	1179	0	0
T11	413559	786944	0	0
T15	2277	0	0	0
T16	365338	9829	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	120093	0	0
T25	128388	0	0	0
T26	0	543229	0	0
T39	0	8839	0	0
T40	211262	0	0	0
T54	0	222	0	0
T67	0	786944	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T65,T66
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T19,T69
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T65,T66
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T18

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T69
1	0	Covered	T4,T5,T18
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412712982	1835268	0	0
DepthKnown_A	412712982	411866862	0	0
RvalidKnown_A	412712982	411866862	0	0
WreadyKnown_A	412712982	411866862	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412712982	1835268	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	1835268	0	0
T4	818334	8449	0	0
T5	346585	37246	0	0
T6	5739	76	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	9	0	0
T19	0	40075	0	0
T20	0	8	0	0
T25	128388	0	0	0
T34	0	174	0	0
T40	211262	0	0	0
T55	0	7	0	0
T56	0	93	0	0
T61	0	7	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	1835268	0	0
T4	818334	8449	0	0
T5	346585	37246	0	0
T6	5739	76	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	9	0	0
T19	0	40075	0	0
T20	0	8	0	0
T25	128388	0	0	0
T34	0	174	0	0
T40	211262	0	0	0
T55	0	7	0	0
T56	0	93	0	0
T61	0	7	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412712982	49904509	0	0
DepthKnown_A	412712982	411866862	0	0
RvalidKnown_A	412712982	411866862	0	0
WreadyKnown_A	412712982	411866862	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412712982	49904509	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	49904509	0	0
T1	489410	44796	0	0
T2	885	128	0	0
T3	3936	832	0	0
T4	818334	645146	0	0
T5	346585	91502	0	0
T10	130627	128	0	0
T11	413559	530688	0	0
T15	2277	256	0	0
T16	365338	823	0	0
T17	1772	256	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	49904509	0	0
T1	489410	44796	0	0
T2	885	128	0	0
T3	3936	832	0	0
T4	818334	645146	0	0
T5	346585	91502	0	0
T10	130627	128	0	0
T11	413559	530688	0	0
T15	2277	256	0	0
T16	365338	823	0	0
T17	1772	256	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412712982	12107764	0	0
DepthKnown_A	412712982	411866862	0	0
RvalidKnown_A	412712982	411866862	0	0
WreadyKnown_A	412712982	411866862	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412712982	12107764	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	12107764	0	0
T1	489410	20872	0	0
T2	885	64	0	0
T3	3936	416	0	0
T4	818334	12619	0	0
T5	346585	22483	0	0
T10	130627	64	0	0
T11	413559	265344	0	0
T15	2277	128	0	0
T16	365338	309	0	0
T17	1772	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	12107764	0	0
T1	489410	20872	0	0
T2	885	64	0	0
T3	3936	416	0	0
T4	818334	12619	0	0
T5	346585	22483	0	0
T10	130627	64	0	0
T11	413559	265344	0	0
T15	2277	128	0	0
T16	365338	309	0	0
T17	1772	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T55,T61,T62
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T16
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412887629	10412029	0	0
DepthKnown_A	412887629	412041509	0	0
RvalidKnown_A	412887629	412041509	0	0
WreadyKnown_A	412887629	412041509	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412887629	10412029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	10412029	0	0
T1	489410	20872	0	0
T2	885	64	0	0
T3	3936	416	0	0
T4	818334	1681	0	0
T5	346585	64	0	0
T10	130627	64	0	0
T11	413559	265344	0	0
T15	2277	128	0	0
T16	365338	64	0	0
T17	1772	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	412041509	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412887629	10412029	0	0
T1	489410	20872	0	0
T2	885	64	0	0
T3	3936	416	0	0
T4	818334	1681	0	0
T5	346585	64	0	0
T10	130627	64	0	0
T11	413559	265344	0	0
T15	2277	128	0	0
T16	365338	64	0	0
T17	1772	128	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T5,T19,T69
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T6

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T19,T69
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	412712982	1572738	0	0
DepthKnown_A	412712982	411866862	0	0
RvalidKnown_A	412712982	411866862	0	0
WreadyKnown_A	412712982	411866862	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	412712982	1572738	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	1572738	0	0
T4	818334	7971	0	0
T5	346585	42685	0	0
T6	5739	85	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	46106	0	0
T21	0	11	0	0
T25	128388	0	0	0
T34	0	230	0	0
T40	211262	0	0	0
T41	0	3	0	0
T55	0	3	0	0
T57	0	21	0	0
T61	0	17	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	411866862	0	0
T1	489410	471234	0	0
T2	885	798	0	0
T3	3936	3253	0	0
T4	818334	818184	0	0
T5	346585	346529	0	0
T10	130627	130482	0	0
T11	413559	413543	0	0
T15	2277	2171	0	0
T16	365338	365240	0	0
T17	1772	1637	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	412712982	1572738	0	0
T4	818334	7971	0	0
T5	346585	42685	0	0
T6	5739	85	0	0
T11	413559	0	0	0
T15	2277	0	0	0
T16	365338	0	0	0
T17	1772	0	0	0
T18	5189	0	0	0
T19	0	46106	0	0
T21	0	11	0	0
T25	128388	0	0	0
T34	0	230	0	0
T40	211262	0	0	0
T41	0	3	0	0
T55	0	3	0	0
T57	0	21	0	0
T61	0	17	0	0