Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22248543	1		T1	157		T2	11201		T3	137
full_word	6339795	1		T1	2		T2	8711		T3	56

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	28588038	1		T1	159		T2	19912		T3	193
auto[TlIntgErrCmd]	102	1		T183	6		T240	8		T248	7
auto[TlIntgErrData]	107	1		T183	10		T240	8		T248	6
auto[TlIntgErrBoth]	91	1		T183	4		T240	4		T248	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	24758536	1		T1	150		T2	16860		T3	58
auto[1]	3829802	1		T1	9		T2	3052		T3	135

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21772886	1		T1	149		T2	10385		T3	58
auto[TlIntgErrNone]	partial	auto[1]	475378	1		T1	8		T2	816		T3	79
auto[TlIntgErrNone]	full_word	auto[0]	2985515	1		T1	1		T2	6475		T6	116
auto[TlIntgErrNone]	full_word	auto[1]	3354259	1		T1	1		T2	2236		T3	56
auto[TlIntgErrCmd]	partial	auto[0]	40	1		T183	4		T240	3		T248	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T183	2		T240	5		T248	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T248	1		T361	1		T369	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T361	1		T370	2		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1		T183	5		T240	5		T248	3
auto[TlIntgErrData]	partial	auto[1]	55	1		T183	5		T240	3		T248	1
auto[TlIntgErrData]	full_word	auto[0]	5	1		T282	1		T363	1		T371	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T248	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T183	2		T240	2		T248	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T183	2		T240	2		T248	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T361	1		T372	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T370	1		T367	1		T362	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20605	1		T185	1140		T186	701		T182	16
full_word	2791322	1		T2	16251		T20	90		T8	354

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	2811646	1		T2	16251		T20	90		T8	354
auto[TlIntgErrCmd]	94	1		T183	3		T240	3		T248	6
auto[TlIntgErrData]	110	1		T183	11		T240	7		T248	5
auto[TlIntgErrBoth]	77	1		T183	6		T240	9		T248	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2786229	1		T2	16251		T20	90		T8	354
auto[1]	25698	1		T185	1324		T186	889		T182	15

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1408	1		T185	54		T186	74		T182	3
auto[TlIntgErrNone]	partial	auto[1]	18944	1		T185	1086		T186	627		T182	13
auto[TlIntgErrNone]	full_word	auto[0]	2784704	1		T2	16251		T20	90		T8	354
auto[TlIntgErrNone]	full_word	auto[1]	6590	1		T185	238		T186	262		T182	2
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T183	2		T240	1		T248	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T183	1		T240	2		T248	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T248	1		T370	2		T367	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T361	1		T370	1		T372	1
auto[TlIntgErrData]	partial	auto[0]	56	1		T183	6		T240	5		T248	5
auto[TlIntgErrData]	partial	auto[1]	41	1		T183	3		T240	1		T285	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T240	1		T275	1		T370	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T183	2		T285	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	23	1		T183	3		T240	2		T248	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T183	2		T240	6		T248	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T183	1		T240	1		T372	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T364	1		-	-		-	-