Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T37
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T37
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1593982940	1590513512	0	0
CheckNGreaterZero_A	3924	3924	0	0
GntImpliesReady_A	1593982940	440275413	0	0
GntImpliesValid_A	1593982940	440275413	0	0
GrantKnown_A	1593982940	1590513512	0	0
IdxKnown_A	1593982940	1590513512	0	0
IndexIsCorrect_A	1593982940	440275413	0	0
NoReadyValidNoGrant_A	1593982940	166579978	0	0
Priority_A	1593982940	462784585	0	0
ReadyAndValidImplyGrant_A	1593982940	440275413	0	0
ReqAndReadyImplyGrant_A	1593982940	440275413	0	0
ReqImpliesValid_A	1593982940	462784585	0	0
ValidKnown_A	1593982940	1590513512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	1590513512	0	0
T1	13808	11276	0	0
T2	198932	198548	0	0
T3	10912	10644	0	0
T4	6628	6424	0	0
T5	749776	721748	0	0
T6	418676	316824	0	0
T7	424044	407408	0	0
T13	14428	11796	0	0
T17	1927056	1926424	0	0
T18	13576	10896	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3924	3924	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T13	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	440275413	0	0
T1	6904	368	0	0
T2	198932	44498	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	38	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	440275413	0	0
T1	6904	368	0	0
T2	198932	44498	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	38	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	1590513512	0	0
T1	13808	11276	0	0
T2	198932	198548	0	0
T3	10912	10644	0	0
T4	6628	6424	0	0
T5	749776	721748	0	0
T6	418676	316824	0	0
T7	424044	407408	0	0
T13	14428	11796	0	0
T17	1927056	1926424	0	0
T18	13576	10896	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	1590513512	0	0
T1	13808	11276	0	0
T2	198932	198548	0	0
T3	10912	10644	0	0
T4	6628	6424	0	0
T5	749776	721748	0	0
T6	418676	316824	0	0
T7	424044	407408	0	0
T13	14428	11796	0	0
T17	1927056	1926424	0	0
T18	13576	10896	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	440275413	0	0
T1	6904	368	0	0
T2	198932	44498	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	38	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	166579978	0	0
T1	6904	1372	0	0
T2	198932	59042	0	0
T3	10912	256	0	0
T4	6628	256	0	0
T5	749776	34496	0	0
T6	418676	5124	0	0
T7	424044	20992	0	0
T8	0	1554	0	0
T9	0	50	0	0
T13	14428	1536	0	0
T17	1927056	256	0	0
T18	13576	1116	0	0
T19	20822	0	0	0
T20	0	118	0	0
T21	0	1002	0	0
T23	0	1020	0	0
T35	0	1222	0	0
T43	0	478	0	0
T56	0	28	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	462784585	0	0
T1	6904	368	0	0
T2	198932	55748	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	44	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	440275413	0	0
T1	6904	368	0	0
T2	198932	44498	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	38	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	440275413	0	0
T1	6904	368	0	0
T2	198932	44498	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	38	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	462784585	0	0
T1	6904	368	0	0
T2	198932	55748	0	0
T3	10912	64	0	0
T4	6628	952	0	0
T5	749776	122752	0	0
T6	418676	0	0	0
T7	424044	76200	0	0
T8	0	1042	0	0
T9	0	44	0	0
T13	14428	396	0	0
T17	1927056	1078	0	0
T18	13576	292	0	0
T19	20822	15578	0	0
T20	0	135684	0	0
T22	0	269404	0	0
T35	0	540820	0	0
T43	0	137036	0	0
T55	0	6	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1593982940	1590513512	0	0
T1	13808	11276	0	0
T2	198932	198548	0	0
T3	10912	10644	0	0
T4	6628	6424	0	0
T5	749776	721748	0	0
T6	418676	316824	0	0
T7	424044	407408	0	0
T13	14428	11796	0	0
T17	1927056	1926424	0	0
T18	13576	10896	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T37,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T37,T61
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398495735	397628378	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	398495735	122328013	0	0
GntImpliesValid_A	398495735	122328013	0	0
GrantKnown_A	398495735	397628378	0	0
IdxKnown_A	398495735	397628378	0	0
IndexIsCorrect_A	398495735	122328013	0	0
NoReadyValidNoGrant_A	398495735	43854877	0	0
Priority_A	398495735	128297807	0	0
ReadyAndValidImplyGrant_A	398495735	122328013	0	0
ReqAndReadyImplyGrant_A	398495735	122328013	0	0
ReqImpliesValid_A	398495735	128297807	0	0
ValidKnown_A	398495735	397628378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122328013	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122328013	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122328013	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	43854877	0	0
T1	3452	686	0	0
T2	49733	13434	0	0
T3	2728	128	0	0
T4	1657	128	0	0
T5	187444	17248	0	0
T6	104669	1228	0	0
T7	106011	10496	0	0
T13	3607	768	0	0
T17	481764	128	0	0
T18	3394	558	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	128297807	0	0
T1	3452	184	0	0
T2	49733	13058	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122328013	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122328013	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	128297807	0	0
T1	3452	184	0	0
T2	49733	13058	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T20,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T37,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T20,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T37,T61
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T20,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398495735	397628378	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	398495735	122081030	0	0
GntImpliesValid_A	398495735	122081030	0	0
GrantKnown_A	398495735	397628378	0	0
IdxKnown_A	398495735	397628378	0	0
IndexIsCorrect_A	398495735	122081030	0	0
NoReadyValidNoGrant_A	398495735	43854901	0	0
Priority_A	398495735	128050800	0	0
ReadyAndValidImplyGrant_A	398495735	122081030	0	0
ReqAndReadyImplyGrant_A	398495735	122081030	0	0
ReqImpliesValid_A	398495735	128050800	0	0
ValidKnown_A	398495735	397628378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122081030	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122081030	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122081030	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	43854901	0	0
T1	3452	686	0	0
T2	49733	13434	0	0
T3	2728	128	0	0
T4	1657	128	0	0
T5	187444	17248	0	0
T6	104669	1228	0	0
T7	106011	10496	0	0
T13	3607	768	0	0
T17	481764	128	0	0
T18	3394	558	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	128050800	0	0
T1	3452	184	0	0
T2	49733	13058	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122081030	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	122081030	0	0
T1	3452	184	0	0
T2	49733	10254	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	128050800	0	0
T1	3452	184	0	0
T2	49733	13058	0	0
T3	2728	32	0	0
T4	1657	32	0	0
T5	187444	61376	0	0
T6	104669	0	0	0
T7	106011	38100	0	0
T13	3607	198	0	0
T17	481764	539	0	0
T18	3394	146	0	0
T19	0	2152	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T19
1	0	Covered	T2,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T37
1	0	Covered	T2,T4,T19
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T37
1	1	Covered	T2,T4,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398495735	397628378	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	398495735	97933185	0	0
GntImpliesValid_A	398495735	97933185	0	0
GrantKnown_A	398495735	397628378	0	0
IdxKnown_A	398495735	397628378	0	0
IndexIsCorrect_A	398495735	97933185	0	0
NoReadyValidNoGrant_A	398495735	39435100	0	0
Priority_A	398495735	103217989	0	0
ReadyAndValidImplyGrant_A	398495735	97933185	0	0
ReqAndReadyImplyGrant_A	398495735	97933185	0	0
ReqImpliesValid_A	398495735	103217989	0	0
ValidKnown_A	398495735	397628378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	39435100	0	0
T2	49733	16087	0	0
T3	2728	0	0	0
T4	1657	0	0	0
T5	187444	0	0	0
T6	104669	1334	0	0
T7	106011	0	0	0
T8	0	777	0	0
T9	0	25	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	0	0	0
T20	0	59	0	0
T21	0	501	0	0
T23	0	510	0	0
T35	0	611	0	0
T43	0	239	0	0
T56	0	14	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	103217989	0	0
T2	49733	14816	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	22	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	103217989	0	0
T2	49733	14816	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	22	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T19
1	0	Covered	T2,T8,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T8,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T37
1	0	Covered	T2,T4,T19
1	1	Covered	T2,T8,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T8,T9
1	1	Covered	T2,T4,T19

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T9,T37
1	1	Covered	T2,T4,T19

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T8,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	398495735	397628378	0	0
CheckNGreaterZero_A	981	981	0	0
GntImpliesReady_A	398495735	97933185	0	0
GntImpliesValid_A	398495735	97933185	0	0
GrantKnown_A	398495735	397628378	0	0
IdxKnown_A	398495735	397628378	0	0
IndexIsCorrect_A	398495735	97933185	0	0
NoReadyValidNoGrant_A	398495735	39435100	0	0
Priority_A	398495735	103217989	0	0
ReadyAndValidImplyGrant_A	398495735	97933185	0	0
ReqAndReadyImplyGrant_A	398495735	97933185	0	0
ReqImpliesValid_A	398495735	103217989	0	0
ValidKnown_A	398495735	397628378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	981	981	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	39435100	0	0
T2	49733	16087	0	0
T3	2728	0	0	0
T4	1657	0	0	0
T5	187444	0	0	0
T6	104669	1334	0	0
T7	106011	0	0	0
T8	0	777	0	0
T9	0	25	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	0	0	0
T20	0	59	0	0
T21	0	501	0	0
T23	0	510	0	0
T35	0	611	0	0
T43	0	239	0	0
T56	0	14	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	103217989	0	0
T2	49733	14816	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	22	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	97933185	0	0
T2	49733	11995	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	19	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	103217989	0	0
T2	49733	14816	0	0
T3	2728	0	0	0
T4	1657	444	0	0
T5	187444	0	0	0
T6	104669	0	0	0
T7	106011	0	0	0
T8	0	521	0	0
T9	0	22	0	0
T13	3607	0	0	0
T17	481764	0	0	0
T18	3394	0	0	0
T19	10411	5637	0	0
T20	0	67842	0	0
T22	0	134702	0	0
T35	0	270410	0	0
T43	0	68518	0	0
T55	0	3	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	398495735	397628378	0	0
T1	3452	2819	0	0
T2	49733	49637	0	0
T3	2728	2661	0	0
T4	1657	1606	0	0
T5	187444	180437	0	0
T6	104669	79206	0	0
T7	106011	101852	0	0
T13	3607	2949	0	0
T17	481764	481606	0	0
T18	3394	2724	0	0