Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	311020	1		T1	2		T2	1		T3	1
all_values[1]	311020	1		T1	2		T2	1		T3	1
all_values[2]	311020	1		T1	2		T2	1		T3	1
all_values[3]	311020	1		T1	2		T2	1		T3	1
all_values[4]	311020	1		T1	2		T2	1		T3	1
all_values[5]	311020	1		T1	2		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	628483	1		T1	12		T2	6		T3	6
auto[1]	1237637	1		T6	24704		T7	38000		T25	3768

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	908618	1		T1	7		T2	4		T3	4
auto[1]	957502	1		T1	5		T2	2		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	310843	1		T1	2		T2	1		T3	1
all_values[0]	auto[1]	auto[1]	177	1		T273	2		T274	5		T338	5
all_values[1]	auto[0]	auto[1]	310858	1		T1	2		T2	1		T3	1
all_values[1]	auto[1]	auto[1]	162	1		T273	1		T274	4		T338	5
all_values[2]	auto[0]	auto[0]	1631	1		T1	2		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	61	1		T273	2		T340	2		T339	1
all_values[2]	auto[1]	auto[0]	309275	1		T6	6176		T7	9500		T25	942
all_values[2]	auto[1]	auto[1]	53	1		T273	1		T274	2		T340	1
all_values[3]	auto[0]	auto[0]	1633	1		T1	2		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	71	1		T273	1		T274	2		T340	1
all_values[3]	auto[1]	auto[0]	72278	1		T6	328		T7	10		T25	942
all_values[3]	auto[1]	auto[1]	237038	1		T6	5848		T7	9490		T35	1062
all_values[4]	auto[0]	auto[0]	1163	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	533	1		T1	1		T4	1		T5	1
all_values[4]	auto[1]	auto[0]	211839	1		T6	5445		T7	8335		T25	1
all_values[4]	auto[1]	auto[1]	97485	1		T6	731		T7	1165		T25	941
all_values[5]	auto[0]	auto[0]	1529	1		T1	2		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	161	1		T8	1		T36	1		T37	1
all_values[5]	auto[1]	auto[0]	309270	1		T6	6176		T7	9500		T25	942
all_values[5]	auto[1]	auto[1]	60	1		T273	2		T274	2		T338	2