Design Module List
dashboard | hierarchy | modlist | groups | tests | asserts
Total Module Definition Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.56 92.94 94.07 98.67 91.84 96.72 99.11


Total modules in report: 79
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
flash_ctrl_region_cfg 52.96 52.96
tlul_lc_gate 74.63 88.24 94.44 57.14 83.33 50.00
prim_generic_flash 80.00 80.00
  flash_ctrl_info_cfg 84.82 69.64 100.00
flash_ctrl_phy_cov_if 89.51 100.00 85.19 83.33
  prim_intr_hw 90.35 95.00 76.39 90.00 100.00
  tlul_adapter_sram 91.98 95.76 75.88 96.30 100.00
flash_phy_erase 92.22 100.00 88.89 100.00 80.00
prim_subreg_shadow 93.27 100.00 73.08 100.00 100.00
  prim_fifo_sync 93.34 100.00 73.38 100.00 100.00
prim_generic_flash_bank 93.55 96.48 92.86 93.75 91.11
flash_phy 93.89 97.67 84.00 100.00
flash_phy_rd_buffers 94.64 100.00 78.57 100.00 100.00
prim_generic_ram_1p 95.24 85.71 100.00 100.00
flash_phy_scramble 95.40 100.00 86.21 100.00
  tlul_rsp_intg_gen 95.42 90.83 100.00
  prim_count 95.76 95.76
flash_ctrl_lcmgr 96.05 99.17 94.79 89.47 96.81 100.00
flash_phy_core 96.55 97.75 91.51 100.00 93.48 100.00
flash_phy_rd_buf_dep 96.59 100.00 86.36 100.00 100.00
flash_ctrl_rd 96.86 100.00 96.97 100.00 90.48
prim_arbiter_fixed 96.88 87.50 100.00 100.00 100.00
flash_ctrl_prog 97.17 100.00 97.06 94.44
prim_sync_reqack 97.22 97.22 100.00 91.67 100.00
tlul_socket_1n 97.25 100.00 93.33 95.65 100.00
flash_ctrl 97.34 97.12 92.80 98.44 100.00 98.33
  prim_arbiter_tree 97.51 96.15 93.88 100.00 100.00
tlul_adapter_reg 97.96 100.00 91.84 100.00 100.00
flash_phy_rd 97.97 100.00 91.87 100.00 100.00
  prim_fifo_sync_cnt 98.03 97.43 96.67 100.00
  prim_arbiter_tree_dup 98.33 95.00 100.00 100.00
flash_phy_prog 98.35 100.00 95.38 100.00 96.36 100.00
tlul_err_resp 98.48 100.00 95.45 100.00
flash_mp 99.28 100.00 97.12 100.00 100.00
tlul_assert 99.65 100.00 100.00 98.95
flash_ctrl_core_reg_top 99.82 100.00 99.26 100.00 100.00
  prim_lc_sync 100.00 100.00 100.00
flash_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
tlul_data_integ_dec 100.00 100.00
  flash_mp_data_region_sel 100.00 100.00 100.00 100.00
prim_sparse_fsm_flop 100.00 100.00 100.00
tlul_cmd_intg_chk 100.00 100.00 100.00
prim_secded_hamming_76_68_enc 100.00 100.00
prim_alert_sender 100.00 100.00
prim_generic_and2 100.00 100.00
prim_mubi4_sender 100.00 100.00 100.00 100.00
tlul_fifo_sync 100.00 100.00 100.00
  prim_onehot_check 100.00 100.00
  prim_subreg 100.00 100.00 100.00 100.00
prim_gf_mult 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_39_32_dec 100.00 100.00
prim_generic_buf 100.00 100.00
  prim_subreg_arb 100.00 100.00 100.00 100.00
prim_subreg_ext 100.00 100.00
flash_ctrl_core_csr_assert_fpv 100.00 100.00
prim_secded_inv_39_32_enc 100.00 100.00
prim_secded_hamming_76_68_dec 100.00 100.00 100.00
flash_ctrl_erase 100.00 100.00 100.00 100.00
tlul_sram_byte 100.00 100.00
tlul_err 100.00 100.00 100.00 100.00 100.00
prim_lfsr 100.00 100.00
flash_ctrl_prim_reg_top 100.00 100.00 100.00 100.00 100.00
prim_secded_inv_64_57_enc 100.00 100.00
prim_secded_inv_64_57_dec 100.00 100.00
prim_prince 100.00 100.00
prim_generic_flop 100.00 100.00 100.00
  prim_mubi4_sync 100.00 100.00 100.00
prim_secded_hamming_72_64_enc 100.00 100.00
prim_flash
tlul_data_integ_enc
prim_reg_we_check
prim_blanker
prim_buf
prim_flop
prim_flop_2sync
tb
prim_and2
prim_sec_anchor_buf
prim_ram_1p