Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T1 |
3 |
|
T241 |
4 |
|
T134 |
1 |
| others[1] |
100 |
1 |
|
T1 |
3 |
|
T241 |
4 |
|
T134 |
1 |
| others[2] |
101 |
1 |
|
T1 |
2 |
|
T239 |
1 |
|
T227 |
1 |
| others[3] |
178 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T44 |
1 |
| false |
43 |
1 |
|
T241 |
2 |
|
T82 |
3 |
|
T120 |
1 |
| true |
6388 |
1 |
|
T1 |
89 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
199 |
1 |
|
T1 |
6 |
|
T17 |
1 |
|
T71 |
1 |
| others[1] |
238 |
1 |
|
T1 |
8 |
|
T7 |
1 |
|
T8 |
1 |
| others[2] |
236 |
1 |
|
T1 |
13 |
|
T241 |
11 |
|
T293 |
1 |
| others[3] |
421 |
1 |
|
T1 |
19 |
|
T26 |
1 |
|
T27 |
1 |
| false |
121 |
1 |
|
T1 |
5 |
|
T73 |
1 |
|
T241 |
6 |
| true |
5695 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1099 |
1 |
|
T1 |
23 |
|
T26 |
1 |
|
T44 |
1 |
| others[1] |
1048 |
1 |
|
T1 |
19 |
|
T6 |
1 |
|
T192 |
1 |
| others[2] |
1053 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T5 |
1 |
| others[3] |
1747 |
1 |
|
T1 |
29 |
|
T2 |
1 |
|
T7 |
1 |
| false |
571 |
1 |
|
T1 |
9 |
|
T75 |
1 |
|
T71 |
1 |
| true |
1392 |
1 |
|
T13 |
1 |
|
T54 |
1 |
|
T136 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T17 |
1 |
| others[1] |
202 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T227 |
1 |
| others[2] |
229 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T26 |
1 |
| others[3] |
386 |
1 |
|
T1 |
21 |
|
T227 |
1 |
|
T41 |
1 |
| false |
112 |
1 |
|
T1 |
5 |
|
T7 |
1 |
|
T20 |
1 |
| true |
5737 |
1 |
|
T1 |
46 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T1 |
11 |
|
T239 |
1 |
|
T241 |
16 |
| others[1] |
214 |
1 |
|
T1 |
10 |
|
T44 |
1 |
|
T241 |
7 |
| others[2] |
212 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T227 |
1 |
| others[3] |
371 |
1 |
|
T1 |
17 |
|
T37 |
1 |
|
T241 |
12 |
| false |
100 |
1 |
|
T1 |
1 |
|
T36 |
1 |
|
T241 |
2 |
| true |
5758 |
1 |
|
T1 |
55 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1287 |
1 |
|
T1 |
21 |
|
T35 |
1 |
|
T227 |
1 |
| others[1] |
1235 |
1 |
|
T1 |
19 |
|
T227 |
1 |
|
T22 |
1 |
| others[2] |
1233 |
1 |
|
T1 |
23 |
|
T19 |
1 |
|
T101 |
1 |
| others[3] |
2106 |
1 |
|
T1 |
32 |
|
T4 |
1 |
|
T6 |
1 |
| false |
621 |
1 |
|
T1 |
6 |
|
T192 |
1 |
|
T25 |
1 |
| true |
428 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T1 |
18 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
1313 |
1 |
|
T1 |
22 |
|
T13 |
1 |
|
T25 |
1 |
| others[2] |
1223 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
2050 |
1 |
|
T1 |
29 |
|
T6 |
1 |
|
T35 |
1 |
| false |
661 |
1 |
|
T1 |
12 |
|
T173 |
7 |
|
T241 |
9 |
| true |
422 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
112 |
1 |
|
T1 |
6 |
|
T227 |
1 |
|
T391 |
1 |
| others[1] |
106 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T72 |
1 |
| others[2] |
97 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T241 |
4 |
| others[3] |
162 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T227 |
1 |
| false |
58 |
1 |
|
T1 |
1 |
|
T241 |
1 |
|
T82 |
2 |
| true |
6375 |
1 |
|
T1 |
73 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
267 |
1 |
|
T1 |
13 |
|
T8 |
1 |
|
T241 |
8 |
| others[1] |
232 |
1 |
|
T1 |
10 |
|
T238 |
1 |
|
T391 |
1 |
| others[2] |
251 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T44 |
1 |
| others[3] |
411 |
1 |
|
T1 |
16 |
|
T36 |
1 |
|
T239 |
1 |
| false |
133 |
1 |
|
T1 |
10 |
|
T241 |
7 |
|
T76 |
1 |
| true |
5616 |
1 |
|
T1 |
45 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1023 |
1 |
|
T1 |
20 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
1052 |
1 |
|
T1 |
16 |
|
T8 |
1 |
|
T37 |
1 |
| others[2] |
1073 |
1 |
|
T1 |
20 |
|
T5 |
1 |
|
T6 |
1 |
| others[3] |
1778 |
1 |
|
T1 |
34 |
|
T4 |
1 |
|
T12 |
1 |
| false |
556 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T7 |
1 |
| true |
1428 |
1 |
|
T17 |
1 |
|
T13 |
1 |
|
T54 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T1 |
13 |
|
T116 |
1 |
|
T241 |
9 |
| others[1] |
234 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T241 |
13 |
| others[2] |
234 |
1 |
|
T1 |
10 |
|
T241 |
7 |
|
T390 |
1 |
| others[3] |
373 |
1 |
|
T1 |
12 |
|
T26 |
1 |
|
T241 |
15 |
| false |
120 |
1 |
|
T1 |
4 |
|
T241 |
8 |
|
T76 |
1 |
| true |
5726 |
1 |
|
T1 |
58 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
210 |
1 |
|
T1 |
10 |
|
T44 |
1 |
|
T227 |
1 |
| others[1] |
246 |
1 |
|
T1 |
12 |
|
T241 |
11 |
|
T82 |
16 |
| others[2] |
231 |
1 |
|
T1 |
12 |
|
T41 |
1 |
|
T241 |
13 |
| others[3] |
339 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T391 |
1 |
| false |
125 |
1 |
|
T1 |
7 |
|
T241 |
3 |
|
T82 |
4 |
| true |
5759 |
1 |
|
T1 |
43 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T1 |
27 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
1225 |
1 |
|
T1 |
17 |
|
T6 |
1 |
|
T44 |
1 |
| others[2] |
1227 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T173 |
10 |
| others[3] |
2121 |
1 |
|
T1 |
27 |
|
T25 |
1 |
|
T101 |
1 |
| false |
641 |
1 |
|
T1 |
10 |
|
T117 |
1 |
|
T173 |
9 |
| true |
442 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1337 |
1 |
|
T1 |
14 |
|
T117 |
1 |
|
T173 |
14 |
| others[1] |
1240 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T101 |
1 |
| others[2] |
1208 |
1 |
|
T1 |
19 |
|
T6 |
1 |
|
T20 |
1 |
| others[3] |
2033 |
1 |
|
T1 |
39 |
|
T25 |
1 |
|
T44 |
1 |
| false |
672 |
1 |
|
T1 |
11 |
|
T173 |
7 |
|
T241 |
9 |
| true |
420 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T1 |
5 |
|
T20 |
1 |
|
T227 |
1 |
| others[1] |
94 |
1 |
|
T1 |
2 |
|
T73 |
1 |
|
T241 |
3 |
| others[2] |
110 |
1 |
|
T1 |
3 |
|
T70 |
1 |
|
T241 |
6 |
| others[3] |
166 |
1 |
|
T1 |
9 |
|
T44 |
1 |
|
T227 |
1 |
| false |
65 |
1 |
|
T1 |
3 |
|
T238 |
1 |
|
T235 |
1 |
| true |
6358 |
1 |
|
T1 |
79 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T1 |
10 |
|
T7 |
1 |
|
T241 |
5 |
| others[1] |
210 |
1 |
|
T1 |
10 |
|
T238 |
1 |
|
T241 |
9 |
| others[2] |
253 |
1 |
|
T1 |
12 |
|
T71 |
1 |
|
T227 |
1 |
| others[3] |
422 |
1 |
|
T1 |
13 |
|
T241 |
21 |
|
T179 |
2 |
| false |
111 |
1 |
|
T1 |
9 |
|
T241 |
11 |
|
T82 |
4 |
| true |
5682 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1059 |
1 |
|
T1 |
25 |
|
T20 |
1 |
|
T8 |
1 |
| others[1] |
1089 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T37 |
1 |
| others[2] |
1031 |
1 |
|
T1 |
19 |
|
T19 |
1 |
|
T239 |
1 |
| others[3] |
1743 |
1 |
|
T1 |
38 |
|
T71 |
1 |
|
T227 |
1 |
| false |
564 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T72 |
1 |
| true |
1424 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T238 |
1 |
| others[1] |
245 |
1 |
|
T1 |
10 |
|
T27 |
1 |
|
T41 |
1 |
| others[2] |
227 |
1 |
|
T1 |
13 |
|
T26 |
1 |
|
T71 |
1 |
| others[3] |
382 |
1 |
|
T1 |
22 |
|
T2 |
1 |
|
T241 |
14 |
| false |
108 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T70 |
1 |
| true |
5692 |
1 |
|
T1 |
40 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
191 |
1 |
|
T1 |
16 |
|
T20 |
1 |
|
T241 |
7 |
| others[1] |
204 |
1 |
|
T1 |
6 |
|
T8 |
1 |
|
T36 |
1 |
| others[2] |
255 |
1 |
|
T1 |
11 |
|
T72 |
1 |
|
T227 |
1 |
| others[3] |
336 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T238 |
1 |
| false |
124 |
1 |
|
T1 |
7 |
|
T241 |
2 |
|
T76 |
1 |
| true |
5800 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T1 |
21 |
|
T35 |
1 |
|
T227 |
1 |
| others[1] |
1322 |
1 |
|
T1 |
22 |
|
T20 |
1 |
|
T44 |
1 |
| others[2] |
1188 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T25 |
1 |
| others[3] |
2112 |
1 |
|
T1 |
34 |
|
T2 |
1 |
|
T4 |
1 |
| false |
625 |
1 |
|
T1 |
10 |
|
T19 |
1 |
|
T173 |
6 |
| true |
444 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T6 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
19 |
|
T2 |
1 |
|
T101 |
1 |
| others[2] |
1222 |
1 |
|
T1 |
14 |
|
T19 |
1 |
|
T35 |
1 |
| others[3] |
2089 |
1 |
|
T1 |
38 |
|
T13 |
1 |
|
T20 |
1 |
| false |
661 |
1 |
|
T1 |
10 |
|
T192 |
1 |
|
T173 |
6 |
| true |
421 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T1 |
4 |
|
T227 |
1 |
|
T41 |
1 |
| others[1] |
113 |
1 |
|
T1 |
6 |
|
T20 |
1 |
|
T44 |
1 |
| others[2] |
129 |
1 |
|
T1 |
5 |
|
T241 |
5 |
|
T134 |
1 |
| others[3] |
163 |
1 |
|
T1 |
5 |
|
T71 |
1 |
|
T227 |
1 |
| false |
46 |
1 |
|
T1 |
1 |
|
T8 |
1 |
|
T241 |
2 |
| true |
6346 |
1 |
|
T1 |
80 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T1 |
10 |
|
T71 |
1 |
|
T241 |
8 |
| others[1] |
242 |
1 |
|
T1 |
13 |
|
T44 |
1 |
|
T41 |
1 |
| others[2] |
243 |
1 |
|
T1 |
7 |
|
T227 |
1 |
|
T118 |
1 |
| others[3] |
413 |
1 |
|
T1 |
17 |
|
T17 |
1 |
|
T8 |
1 |
| false |
129 |
1 |
|
T1 |
6 |
|
T27 |
1 |
|
T239 |
1 |
| true |
5638 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1082 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T6 |
1 |
| others[1] |
1070 |
1 |
|
T1 |
19 |
|
T12 |
1 |
|
T20 |
1 |
| others[2] |
1122 |
1 |
|
T1 |
21 |
|
T5 |
1 |
|
T74 |
1 |
| others[3] |
1714 |
1 |
|
T1 |
27 |
|
T54 |
1 |
|
T27 |
1 |
| false |
553 |
1 |
|
T1 |
15 |
|
T35 |
1 |
|
T22 |
1 |
| true |
1369 |
1 |
|
T2 |
1 |
|
T13 |
1 |
|
T8 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T1 |
10 |
|
T241 |
6 |
|
T179 |
1 |
| others[1] |
228 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T241 |
14 |
| others[2] |
255 |
1 |
|
T1 |
15 |
|
T17 |
1 |
|
T20 |
1 |
| others[3] |
421 |
1 |
|
T1 |
14 |
|
T36 |
1 |
|
T70 |
1 |
| false |
117 |
1 |
|
T1 |
4 |
|
T27 |
1 |
|
T241 |
2 |
| true |
5683 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T1 |
11 |
|
T20 |
1 |
|
T36 |
1 |
| others[1] |
185 |
1 |
|
T1 |
7 |
|
T44 |
1 |
|
T241 |
6 |
| others[2] |
232 |
1 |
|
T1 |
10 |
|
T70 |
1 |
|
T391 |
1 |
| others[3] |
353 |
1 |
|
T1 |
11 |
|
T227 |
2 |
|
T41 |
1 |
| false |
120 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T72 |
1 |
| true |
5784 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T1 |
23 |
|
T6 |
1 |
|
T44 |
1 |
| others[1] |
1227 |
1 |
|
T1 |
14 |
|
T7 |
1 |
|
T192 |
1 |
| others[2] |
1212 |
1 |
|
T1 |
19 |
|
T25 |
1 |
|
T19 |
1 |
| others[3] |
2130 |
1 |
|
T1 |
35 |
|
T4 |
1 |
|
T20 |
1 |
| false |
639 |
1 |
|
T1 |
10 |
|
T2 |
1 |
|
T173 |
4 |
| true |
442 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T1 |
19 |
|
T20 |
1 |
|
T173 |
17 |
| others[1] |
1232 |
1 |
|
T1 |
11 |
|
T35 |
1 |
|
T239 |
1 |
| others[2] |
1259 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T227 |
1 |
| others[3] |
2096 |
1 |
|
T1 |
41 |
|
T192 |
1 |
|
T25 |
1 |
| false |
672 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T173 |
10 |
| true |
425 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
100 |
1 |
|
T1 |
1 |
|
T227 |
1 |
|
T241 |
4 |
| others[1] |
107 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T36 |
1 |
| others[2] |
101 |
1 |
|
T1 |
6 |
|
T241 |
6 |
|
T334 |
1 |
| others[3] |
179 |
1 |
|
T1 |
4 |
|
T227 |
1 |
|
T391 |
1 |
| false |
54 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T44 |
1 |
| true |
6369 |
1 |
|
T1 |
84 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T1 |
10 |
|
T241 |
9 |
|
T134 |
1 |
| others[1] |
237 |
1 |
|
T1 |
9 |
|
T44 |
1 |
|
T118 |
1 |
| others[2] |
252 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T227 |
1 |
| others[3] |
403 |
1 |
|
T1 |
16 |
|
T17 |
1 |
|
T7 |
1 |
| false |
112 |
1 |
|
T1 |
5 |
|
T27 |
1 |
|
T238 |
1 |
| true |
5652 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1055 |
1 |
|
T1 |
16 |
|
T37 |
1 |
|
T35 |
1 |
| others[1] |
1056 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T75 |
1 |
| others[2] |
1046 |
1 |
|
T1 |
18 |
|
T36 |
1 |
|
T71 |
1 |
| others[3] |
1841 |
1 |
|
T1 |
34 |
|
T6 |
1 |
|
T7 |
1 |
| false |
557 |
1 |
|
T1 |
11 |
|
T173 |
9 |
|
T175 |
1 |
| true |
1355 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |