Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T36 |
1 |
| others[1] |
239 |
1 |
|
T1 |
11 |
|
T17 |
1 |
|
T70 |
1 |
| others[2] |
213 |
1 |
|
T1 |
7 |
|
T72 |
1 |
|
T241 |
6 |
| others[3] |
376 |
1 |
|
T1 |
14 |
|
T26 |
1 |
|
T44 |
1 |
| false |
125 |
1 |
|
T1 |
4 |
|
T118 |
1 |
|
T241 |
6 |
| true |
5704 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T1 |
6 |
|
T391 |
1 |
|
T241 |
15 |
| others[1] |
207 |
1 |
|
T1 |
8 |
|
T8 |
1 |
|
T238 |
1 |
| others[2] |
217 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T20 |
1 |
| others[3] |
391 |
1 |
|
T1 |
14 |
|
T72 |
1 |
|
T118 |
1 |
| false |
113 |
1 |
|
T1 |
5 |
|
T239 |
1 |
|
T241 |
5 |
| true |
5741 |
1 |
|
T1 |
61 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1182 |
1 |
|
T1 |
18 |
|
T88 |
1 |
|
T173 |
19 |
| others[1] |
1204 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T192 |
1 |
| others[2] |
1302 |
1 |
|
T1 |
24 |
|
T2 |
1 |
|
T20 |
1 |
| others[3] |
2168 |
1 |
|
T1 |
31 |
|
T6 |
1 |
|
T44 |
1 |
| false |
630 |
1 |
|
T1 |
13 |
|
T173 |
9 |
|
T241 |
8 |
| true |
424 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T1 |
18 |
|
T44 |
1 |
|
T173 |
12 |
| others[1] |
1267 |
1 |
|
T1 |
22 |
|
T2 |
1 |
|
T4 |
1 |
| others[2] |
1220 |
1 |
|
T1 |
26 |
|
T6 |
1 |
|
T239 |
1 |
| others[3] |
2067 |
1 |
|
T1 |
29 |
|
T20 |
1 |
|
T25 |
1 |
| false |
700 |
1 |
|
T1 |
6 |
|
T101 |
1 |
|
T117 |
1 |
| true |
415 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T1 |
3 |
|
T241 |
7 |
|
T76 |
2 |
| others[1] |
106 |
1 |
|
T1 |
5 |
|
T4 |
1 |
|
T71 |
1 |
| others[2] |
104 |
1 |
|
T1 |
3 |
|
T20 |
1 |
|
T227 |
1 |
| others[3] |
190 |
1 |
|
T1 |
11 |
|
T44 |
1 |
|
T37 |
1 |
| false |
39 |
1 |
|
T1 |
2 |
|
T241 |
2 |
|
T76 |
2 |
| true |
6364 |
1 |
|
T1 |
77 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T241 |
8 |
| others[1] |
222 |
1 |
|
T1 |
9 |
|
T20 |
1 |
|
T238 |
1 |
| others[2] |
234 |
1 |
|
T1 |
12 |
|
T241 |
9 |
|
T293 |
1 |
| others[3] |
394 |
1 |
|
T1 |
18 |
|
T27 |
1 |
|
T239 |
1 |
| false |
140 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T70 |
1 |
| true |
5683 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1106 |
1 |
|
T1 |
25 |
|
T238 |
1 |
|
T70 |
1 |
| others[1] |
1078 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T20 |
1 |
| others[2] |
1044 |
1 |
|
T1 |
17 |
|
T6 |
1 |
|
T101 |
1 |
| others[3] |
1734 |
1 |
|
T1 |
31 |
|
T5 |
1 |
|
T25 |
1 |
| false |
600 |
1 |
|
T1 |
10 |
|
T55 |
1 |
|
T35 |
1 |
| true |
1348 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T1 |
13 |
|
T7 |
1 |
|
T241 |
12 |
| others[1] |
212 |
1 |
|
T1 |
7 |
|
T239 |
1 |
|
T72 |
1 |
| others[2] |
258 |
1 |
|
T1 |
11 |
|
T36 |
1 |
|
T41 |
1 |
| others[3] |
403 |
1 |
|
T1 |
18 |
|
T2 |
1 |
|
T17 |
1 |
| false |
133 |
1 |
|
T1 |
2 |
|
T44 |
1 |
|
T241 |
4 |
| true |
5674 |
1 |
|
T1 |
50 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
207 |
1 |
|
T1 |
12 |
|
T391 |
1 |
|
T241 |
8 |
| others[1] |
228 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T70 |
1 |
| others[2] |
230 |
1 |
|
T1 |
6 |
|
T239 |
1 |
|
T241 |
7 |
| others[3] |
382 |
1 |
|
T1 |
15 |
|
T20 |
1 |
|
T241 |
14 |
| false |
126 |
1 |
|
T1 |
3 |
|
T238 |
1 |
|
T241 |
6 |
| true |
5737 |
1 |
|
T1 |
54 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T1 |
23 |
|
T2 |
1 |
|
T20 |
1 |
| others[1] |
1267 |
1 |
|
T1 |
24 |
|
T227 |
1 |
|
T117 |
1 |
| others[2] |
1220 |
1 |
|
T1 |
23 |
|
T22 |
1 |
|
T173 |
13 |
| others[3] |
2062 |
1 |
|
T1 |
28 |
|
T4 |
1 |
|
T6 |
1 |
| false |
661 |
1 |
|
T1 |
3 |
|
T173 |
7 |
|
T175 |
1 |
| true |
435 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1260 |
1 |
|
T1 |
13 |
|
T6 |
1 |
|
T25 |
1 |
| others[1] |
1288 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T101 |
1 |
| others[2] |
1218 |
1 |
|
T1 |
22 |
|
T7 |
1 |
|
T192 |
1 |
| others[3] |
2071 |
1 |
|
T1 |
36 |
|
T2 |
1 |
|
T20 |
1 |
| false |
655 |
1 |
|
T1 |
12 |
|
T173 |
9 |
|
T241 |
12 |
| true |
418 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
2 |
|
T44 |
1 |
|
T241 |
4 |
| others[1] |
104 |
1 |
|
T1 |
7 |
|
T20 |
1 |
|
T118 |
1 |
| others[2] |
106 |
1 |
|
T1 |
6 |
|
T241 |
4 |
|
T134 |
1 |
| others[3] |
187 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T241 |
6 |
| false |
59 |
1 |
|
T1 |
1 |
|
T227 |
2 |
|
T241 |
3 |
| true |
6349 |
1 |
|
T1 |
82 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
274 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T20 |
1 |
| others[1] |
252 |
1 |
|
T1 |
10 |
|
T17 |
1 |
|
T26 |
1 |
| others[2] |
225 |
1 |
|
T1 |
8 |
|
T72 |
1 |
|
T241 |
7 |
| others[3] |
387 |
1 |
|
T1 |
16 |
|
T8 |
1 |
|
T36 |
1 |
| false |
147 |
1 |
|
T1 |
4 |
|
T27 |
1 |
|
T241 |
3 |
| true |
5625 |
1 |
|
T1 |
51 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1094 |
1 |
|
T1 |
20 |
|
T238 |
1 |
|
T72 |
1 |
| others[1] |
1066 |
1 |
|
T1 |
27 |
|
T13 |
1 |
|
T20 |
1 |
| others[2] |
1037 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T101 |
1 |
| others[3] |
1731 |
1 |
|
T1 |
24 |
|
T2 |
1 |
|
T6 |
1 |
| false |
542 |
1 |
|
T1 |
9 |
|
T5 |
1 |
|
T54 |
1 |
| true |
1440 |
1 |
|
T17 |
1 |
|
T12 |
1 |
|
T7 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T1 |
6 |
|
T36 |
1 |
|
T73 |
1 |
| others[1] |
240 |
1 |
|
T1 |
12 |
|
T26 |
1 |
|
T239 |
1 |
| others[2] |
207 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T241 |
5 |
| others[3] |
385 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T70 |
1 |
| false |
110 |
1 |
|
T1 |
4 |
|
T8 |
1 |
|
T118 |
1 |
| true |
5736 |
1 |
|
T1 |
59 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T1 |
5 |
|
T20 |
1 |
|
T241 |
11 |
| others[1] |
214 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T241 |
7 |
| others[2] |
241 |
1 |
|
T1 |
8 |
|
T241 |
14 |
|
T178 |
1 |
| others[3] |
351 |
1 |
|
T1 |
16 |
|
T239 |
1 |
|
T72 |
1 |
| false |
96 |
1 |
|
T1 |
4 |
|
T241 |
4 |
|
T134 |
1 |
| true |
5786 |
1 |
|
T1 |
57 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T1 |
22 |
|
T44 |
1 |
|
T19 |
1 |
| others[1] |
1268 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T173 |
13 |
| others[2] |
1243 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T35 |
1 |
| others[3] |
2056 |
1 |
|
T1 |
32 |
|
T6 |
1 |
|
T25 |
1 |
| false |
648 |
1 |
|
T1 |
11 |
|
T192 |
1 |
|
T173 |
5 |
| true |
451 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1229 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T173 |
13 |
| others[1] |
1232 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T44 |
1 |
| others[2] |
1271 |
1 |
|
T1 |
23 |
|
T20 |
1 |
|
T173 |
15 |
| others[3] |
2099 |
1 |
|
T1 |
37 |
|
T192 |
1 |
|
T25 |
1 |
| false |
656 |
1 |
|
T1 |
12 |
|
T101 |
1 |
|
T173 |
4 |
| true |
423 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T20 |
1 |
| others[1] |
91 |
1 |
|
T1 |
4 |
|
T238 |
1 |
|
T392 |
1 |
| others[2] |
102 |
1 |
|
T1 |
4 |
|
T241 |
4 |
|
T134 |
1 |
| others[3] |
185 |
1 |
|
T1 |
10 |
|
T44 |
1 |
|
T391 |
1 |
| false |
62 |
1 |
|
T1 |
5 |
|
T227 |
2 |
|
T241 |
3 |
| true |
6365 |
1 |
|
T1 |
71 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T1 |
4 |
|
T238 |
1 |
|
T71 |
1 |
| others[1] |
232 |
1 |
|
T1 |
15 |
|
T37 |
1 |
|
T41 |
1 |
| others[2] |
219 |
1 |
|
T1 |
7 |
|
T116 |
1 |
|
T241 |
9 |
| others[3] |
419 |
1 |
|
T1 |
25 |
|
T2 |
1 |
|
T7 |
1 |
| false |
140 |
1 |
|
T1 |
6 |
|
T241 |
2 |
|
T351 |
1 |
| true |
5685 |
1 |
|
T1 |
44 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T1 |
18 |
|
T101 |
1 |
|
T72 |
1 |
| others[1] |
1076 |
1 |
|
T1 |
27 |
|
T5 |
1 |
|
T36 |
1 |
| others[2] |
1084 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T17 |
1 |
| others[3] |
1799 |
1 |
|
T1 |
37 |
|
T4 |
1 |
|
T25 |
1 |
| false |
541 |
1 |
|
T1 |
9 |
|
T20 |
1 |
|
T391 |
1 |
| true |
1375 |
1 |
|
T2 |
1 |
|
T12 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
217 |
1 |
|
T1 |
10 |
|
T239 |
1 |
|
T391 |
1 |
| others[1] |
214 |
1 |
|
T1 |
9 |
|
T71 |
1 |
|
T41 |
1 |
| others[2] |
224 |
1 |
|
T1 |
11 |
|
T7 |
1 |
|
T8 |
1 |
| others[3] |
428 |
1 |
|
T1 |
18 |
|
T70 |
1 |
|
T72 |
1 |
| false |
108 |
1 |
|
T1 |
2 |
|
T17 |
1 |
|
T241 |
4 |
| true |
5719 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T1 |
12 |
|
T36 |
1 |
|
T70 |
1 |
| others[1] |
237 |
1 |
|
T1 |
11 |
|
T241 |
12 |
|
T82 |
15 |
| others[2] |
223 |
1 |
|
T1 |
13 |
|
T241 |
9 |
|
T390 |
1 |
| others[3] |
375 |
1 |
|
T1 |
15 |
|
T8 |
1 |
|
T71 |
1 |
| false |
101 |
1 |
|
T241 |
5 |
|
T76 |
1 |
|
T82 |
8 |
| true |
5754 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1247 |
1 |
|
T1 |
21 |
|
T4 |
1 |
|
T7 |
1 |
| others[1] |
1243 |
1 |
|
T1 |
23 |
|
T227 |
1 |
|
T22 |
1 |
| others[2] |
1276 |
1 |
|
T1 |
23 |
|
T6 |
1 |
|
T20 |
1 |
| others[3] |
2054 |
1 |
|
T1 |
23 |
|
T19 |
1 |
|
T101 |
1 |
| false |
638 |
1 |
|
T1 |
11 |
|
T25 |
1 |
|
T35 |
1 |
| true |
452 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1224 |
1 |
|
T1 |
23 |
|
T2 |
1 |
|
T13 |
1 |
| others[1] |
1271 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T25 |
1 |
| others[2] |
1257 |
1 |
|
T1 |
17 |
|
T19 |
1 |
|
T101 |
1 |
| others[3] |
2085 |
1 |
|
T1 |
42 |
|
T4 |
1 |
|
T192 |
1 |
| false |
639 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T44 |
1 |
| true |
434 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T1 |
3 |
|
T227 |
1 |
|
T391 |
1 |
| others[1] |
131 |
1 |
|
T1 |
5 |
|
T238 |
1 |
|
T70 |
1 |
| others[2] |
122 |
1 |
|
T1 |
6 |
|
T20 |
1 |
|
T37 |
1 |
| others[3] |
181 |
1 |
|
T1 |
9 |
|
T44 |
1 |
|
T241 |
1 |
| false |
60 |
1 |
|
T1 |
2 |
|
T241 |
2 |
|
T134 |
1 |
| true |
6300 |
1 |
|
T1 |
76 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T1 |
9 |
|
T36 |
1 |
|
T227 |
1 |
| others[1] |
238 |
1 |
|
T1 |
5 |
|
T17 |
1 |
|
T37 |
1 |
| others[2] |
232 |
1 |
|
T1 |
12 |
|
T238 |
1 |
|
T241 |
14 |
| others[3] |
381 |
1 |
|
T1 |
24 |
|
T7 |
1 |
|
T239 |
1 |
| false |
131 |
1 |
|
T1 |
5 |
|
T241 |
4 |
|
T33 |
1 |
| true |
5688 |
1 |
|
T1 |
46 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1079 |
1 |
|
T1 |
16 |
|
T36 |
1 |
|
T44 |
1 |
| others[1] |
1008 |
1 |
|
T1 |
20 |
|
T25 |
1 |
|
T101 |
1 |
| others[2] |
1052 |
1 |
|
T1 |
20 |
|
T8 |
1 |
|
T192 |
1 |
| others[3] |
1839 |
1 |
|
T1 |
30 |
|
T4 |
1 |
|
T6 |
1 |
| false |
570 |
1 |
|
T1 |
15 |
|
T54 |
1 |
|
T35 |
1 |
| true |
1362 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T1 |
6 |
|
T36 |
1 |
|
T70 |
1 |
| others[1] |
237 |
1 |
|
T1 |
6 |
|
T20 |
1 |
|
T26 |
1 |
| others[2] |
229 |
1 |
|
T1 |
12 |
|
T37 |
1 |
|
T238 |
1 |
| others[3] |
356 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T116 |
1 |
| false |
138 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T227 |
1 |
| true |
5715 |
1 |
|
T1 |
59 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T1 |
12 |
|
T8 |
1 |
|
T241 |
14 |
| others[1] |
230 |
1 |
|
T1 |
7 |
|
T241 |
8 |
|
T76 |
1 |
| others[2] |
232 |
1 |
|
T1 |
4 |
|
T71 |
1 |
|
T73 |
1 |
| others[3] |
354 |
1 |
|
T1 |
19 |
|
T239 |
1 |
|
T118 |
1 |
| false |
121 |
1 |
|
T1 |
2 |
|
T36 |
1 |
|
T241 |
6 |
| true |
5735 |
1 |
|
T1 |
57 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T1 |
26 |
|
T25 |
1 |
|
T227 |
1 |
| others[1] |
1249 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T44 |
1 |
| others[2] |
1188 |
1 |
|
T1 |
22 |
|
T117 |
1 |
|
T173 |
15 |
| others[3] |
2111 |
1 |
|
T1 |
30 |
|
T4 |
1 |
|
T101 |
1 |
| false |
649 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T192 |
1 |
| true |
444 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |