Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1271 |
1 |
|
T1 |
21 |
|
T6 |
1 |
|
T192 |
1 |
| others[1] |
1225 |
1 |
|
T1 |
15 |
|
T25 |
1 |
|
T227 |
1 |
| others[2] |
1212 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
2089 |
1 |
|
T1 |
33 |
|
T2 |
1 |
|
T20 |
1 |
| false |
690 |
1 |
|
T1 |
12 |
|
T173 |
10 |
|
T241 |
9 |
| true |
423 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T44 |
1 |
| others[1] |
101 |
1 |
|
T1 |
6 |
|
T241 |
3 |
|
T334 |
1 |
| others[2] |
101 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T37 |
1 |
| others[3] |
185 |
1 |
|
T1 |
8 |
|
T118 |
1 |
|
T241 |
10 |
| false |
65 |
1 |
|
T1 |
3 |
|
T8 |
1 |
|
T227 |
1 |
| true |
6353 |
1 |
|
T1 |
82 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T1 |
12 |
|
T239 |
1 |
|
T227 |
1 |
| others[1] |
240 |
1 |
|
T1 |
10 |
|
T116 |
1 |
|
T241 |
10 |
| others[2] |
256 |
1 |
|
T1 |
6 |
|
T7 |
1 |
|
T8 |
1 |
| others[3] |
422 |
1 |
|
T1 |
13 |
|
T17 |
1 |
|
T36 |
1 |
| false |
115 |
1 |
|
T1 |
4 |
|
T26 |
1 |
|
T70 |
1 |
| true |
5663 |
1 |
|
T1 |
56 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T5 |
1 |
| others[1] |
1033 |
1 |
|
T1 |
21 |
|
T72 |
1 |
|
T173 |
13 |
| others[2] |
1025 |
1 |
|
T1 |
20 |
|
T25 |
1 |
|
T54 |
1 |
| others[3] |
1875 |
1 |
|
T1 |
30 |
|
T2 |
1 |
|
T6 |
1 |
| false |
588 |
1 |
|
T1 |
12 |
|
T20 |
1 |
|
T192 |
1 |
| true |
1352 |
1 |
|
T17 |
1 |
|
T8 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
260 |
1 |
|
T1 |
10 |
|
T7 |
1 |
|
T70 |
1 |
| others[1] |
241 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T17 |
1 |
| others[2] |
238 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T73 |
1 |
| others[3] |
398 |
1 |
|
T1 |
19 |
|
T238 |
1 |
|
T391 |
1 |
| false |
114 |
1 |
|
T1 |
3 |
|
T4 |
1 |
|
T227 |
1 |
| true |
5659 |
1 |
|
T1 |
50 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T1 |
9 |
|
T37 |
1 |
|
T238 |
1 |
| others[1] |
205 |
1 |
|
T1 |
6 |
|
T241 |
8 |
|
T390 |
1 |
| others[2] |
226 |
1 |
|
T1 |
12 |
|
T70 |
1 |
|
T227 |
1 |
| others[3] |
376 |
1 |
|
T1 |
11 |
|
T8 |
1 |
|
T239 |
1 |
| false |
102 |
1 |
|
T1 |
8 |
|
T241 |
6 |
|
T392 |
1 |
| true |
5772 |
1 |
|
T1 |
55 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1263 |
1 |
|
T1 |
14 |
|
T36 |
1 |
|
T44 |
1 |
| others[1] |
1274 |
1 |
|
T1 |
23 |
|
T6 |
1 |
|
T25 |
1 |
| others[2] |
1252 |
1 |
|
T1 |
21 |
|
T192 |
1 |
|
T117 |
1 |
| others[3] |
2058 |
1 |
|
T1 |
32 |
|
T20 |
1 |
|
T19 |
1 |
| false |
645 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T173 |
6 |
| true |
418 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1253 |
1 |
|
T1 |
25 |
|
T4 |
1 |
|
T192 |
1 |
| others[1] |
1281 |
1 |
|
T1 |
19 |
|
T20 |
1 |
|
T227 |
1 |
| others[2] |
1294 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T44 |
1 |
| others[3] |
2024 |
1 |
|
T1 |
37 |
|
T173 |
14 |
|
T241 |
28 |
| false |
634 |
1 |
|
T1 |
6 |
|
T25 |
1 |
|
T101 |
1 |
| true |
424 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T1 |
5 |
|
T227 |
1 |
|
T241 |
5 |
| others[1] |
122 |
1 |
|
T1 |
5 |
|
T227 |
1 |
|
T241 |
8 |
| others[2] |
118 |
1 |
|
T1 |
4 |
|
T71 |
1 |
|
T391 |
1 |
| others[3] |
174 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T20 |
1 |
| false |
44 |
1 |
|
T1 |
2 |
|
T241 |
3 |
|
T82 |
1 |
| true |
6350 |
1 |
|
T1 |
84 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T1 |
5 |
|
T70 |
1 |
|
T241 |
15 |
| others[1] |
245 |
1 |
|
T1 |
9 |
|
T8 |
1 |
|
T227 |
1 |
| others[2] |
226 |
1 |
|
T1 |
13 |
|
T227 |
1 |
|
T241 |
12 |
| others[3] |
376 |
1 |
|
T1 |
13 |
|
T7 |
1 |
|
T71 |
1 |
| false |
126 |
1 |
|
T1 |
5 |
|
T241 |
2 |
|
T82 |
5 |
| true |
5684 |
1 |
|
T1 |
56 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1078 |
1 |
|
T1 |
19 |
|
T2 |
1 |
|
T17 |
1 |
| others[1] |
1046 |
1 |
|
T1 |
17 |
|
T8 |
1 |
|
T19 |
1 |
| others[2] |
1094 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
1778 |
1 |
|
T1 |
36 |
|
T12 |
1 |
|
T13 |
1 |
| false |
533 |
1 |
|
T1 |
9 |
|
T35 |
1 |
|
T173 |
8 |
| true |
1381 |
1 |
|
T5 |
1 |
|
T7 |
1 |
|
T26 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
261 |
1 |
|
T1 |
14 |
|
T17 |
1 |
|
T227 |
1 |
| others[1] |
225 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T36 |
1 |
| others[2] |
247 |
1 |
|
T1 |
7 |
|
T227 |
1 |
|
T241 |
13 |
| others[3] |
416 |
1 |
|
T1 |
13 |
|
T8 |
1 |
|
T72 |
1 |
| false |
117 |
1 |
|
T1 |
5 |
|
T241 |
5 |
|
T179 |
1 |
| true |
5644 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T1 |
15 |
|
T36 |
1 |
|
T241 |
6 |
| others[1] |
233 |
1 |
|
T1 |
15 |
|
T8 |
1 |
|
T241 |
5 |
| others[2] |
259 |
1 |
|
T1 |
13 |
|
T391 |
1 |
|
T241 |
11 |
| others[3] |
350 |
1 |
|
T1 |
16 |
|
T238 |
1 |
|
T227 |
1 |
| false |
130 |
1 |
|
T1 |
6 |
|
T71 |
1 |
|
T241 |
8 |
| true |
5725 |
1 |
|
T1 |
36 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T1 |
25 |
|
T4 |
1 |
|
T44 |
1 |
| others[1] |
1254 |
1 |
|
T1 |
15 |
|
T101 |
1 |
|
T173 |
13 |
| others[2] |
1235 |
1 |
|
T1 |
15 |
|
T6 |
1 |
|
T36 |
1 |
| others[3] |
2055 |
1 |
|
T1 |
35 |
|
T7 |
1 |
|
T192 |
1 |
| false |
675 |
1 |
|
T1 |
11 |
|
T20 |
1 |
|
T173 |
5 |
| true |
446 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1274 |
1 |
|
T1 |
22 |
|
T13 |
1 |
|
T25 |
1 |
| others[1] |
1306 |
1 |
|
T1 |
23 |
|
T44 |
1 |
|
T22 |
1 |
| others[2] |
1253 |
1 |
|
T1 |
14 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
2051 |
1 |
|
T1 |
31 |
|
T20 |
1 |
|
T192 |
1 |
| false |
609 |
1 |
|
T1 |
11 |
|
T101 |
1 |
|
T227 |
1 |
| true |
417 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
89 |
1 |
|
T1 |
5 |
|
T20 |
1 |
|
T241 |
4 |
| others[1] |
112 |
1 |
|
T227 |
1 |
|
T41 |
1 |
|
T241 |
4 |
| others[2] |
91 |
1 |
|
T1 |
4 |
|
T118 |
1 |
|
T241 |
1 |
| others[3] |
185 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T72 |
1 |
| false |
70 |
1 |
|
T1 |
2 |
|
T241 |
4 |
|
T76 |
1 |
| true |
6363 |
1 |
|
T1 |
84 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T1 |
8 |
|
T7 |
1 |
|
T26 |
1 |
| others[1] |
236 |
1 |
|
T1 |
15 |
|
T227 |
1 |
|
T241 |
8 |
| others[2] |
216 |
1 |
|
T1 |
5 |
|
T8 |
1 |
|
T241 |
7 |
| others[3] |
403 |
1 |
|
T1 |
13 |
|
T44 |
1 |
|
T37 |
1 |
| false |
119 |
1 |
|
T1 |
7 |
|
T241 |
3 |
|
T76 |
1 |
| true |
5707 |
1 |
|
T1 |
53 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T8 |
1 |
| others[1] |
1036 |
1 |
|
T1 |
16 |
|
T35 |
1 |
|
T173 |
16 |
| others[2] |
1097 |
1 |
|
T1 |
19 |
|
T20 |
1 |
|
T25 |
1 |
| others[3] |
1768 |
1 |
|
T1 |
41 |
|
T6 |
1 |
|
T12 |
1 |
| false |
573 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T19 |
1 |
| true |
1366 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T1 |
6 |
|
T26 |
1 |
|
T116 |
1 |
| others[1] |
208 |
1 |
|
T1 |
8 |
|
T44 |
1 |
|
T239 |
1 |
| others[2] |
241 |
1 |
|
T1 |
9 |
|
T17 |
1 |
|
T27 |
1 |
| others[3] |
391 |
1 |
|
T1 |
21 |
|
T7 |
1 |
|
T241 |
19 |
| false |
105 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T241 |
2 |
| true |
5729 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T70 |
1 |
| others[1] |
234 |
1 |
|
T1 |
9 |
|
T227 |
1 |
|
T241 |
11 |
| others[2] |
187 |
1 |
|
T1 |
12 |
|
T238 |
1 |
|
T241 |
11 |
| others[3] |
361 |
1 |
|
T1 |
15 |
|
T37 |
1 |
|
T71 |
1 |
| false |
125 |
1 |
|
T1 |
8 |
|
T241 |
2 |
|
T76 |
2 |
| true |
5762 |
1 |
|
T1 |
43 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T1 |
26 |
|
T6 |
1 |
|
T101 |
1 |
| others[1] |
1282 |
1 |
|
T1 |
21 |
|
T20 |
1 |
|
T192 |
1 |
| others[2] |
1219 |
1 |
|
T1 |
14 |
|
T5 |
1 |
|
T22 |
1 |
| others[3] |
2111 |
1 |
|
T1 |
28 |
|
T4 |
1 |
|
T25 |
1 |
| false |
642 |
1 |
|
T1 |
12 |
|
T173 |
7 |
|
T241 |
9 |
| true |
434 |
1 |
|
T2 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T1 |
17 |
|
T20 |
1 |
|
T25 |
1 |
| others[1] |
1252 |
1 |
|
T1 |
24 |
|
T6 |
1 |
|
T101 |
1 |
| others[2] |
1246 |
1 |
|
T1 |
17 |
|
T44 |
1 |
|
T227 |
1 |
| others[3] |
2120 |
1 |
|
T1 |
30 |
|
T4 |
1 |
|
T192 |
1 |
| false |
663 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T173 |
8 |
| true |
425 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T1 |
6 |
|
T241 |
5 |
|
T134 |
1 |
| others[1] |
102 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T227 |
1 |
| others[2] |
106 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T241 |
3 |
| others[3] |
154 |
1 |
|
T1 |
5 |
|
T227 |
1 |
|
T241 |
6 |
| false |
64 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T241 |
3 |
| true |
6367 |
1 |
|
T1 |
76 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T1 |
15 |
|
T7 |
1 |
|
T241 |
12 |
| others[1] |
228 |
1 |
|
T1 |
12 |
|
T8 |
1 |
|
T26 |
1 |
| others[2] |
222 |
1 |
|
T1 |
4 |
|
T4 |
1 |
|
T36 |
1 |
| others[3] |
410 |
1 |
|
T1 |
11 |
|
T71 |
1 |
|
T241 |
14 |
| false |
121 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T241 |
5 |
| true |
5676 |
1 |
|
T1 |
55 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
985 |
1 |
|
T1 |
16 |
|
T20 |
1 |
|
T192 |
1 |
| others[1] |
1070 |
1 |
|
T1 |
20 |
|
T4 |
1 |
|
T13 |
1 |
| others[2] |
1090 |
1 |
|
T1 |
22 |
|
T8 |
1 |
|
T35 |
1 |
| others[3] |
1780 |
1 |
|
T1 |
26 |
|
T6 |
1 |
|
T55 |
1 |
| false |
567 |
1 |
|
T1 |
17 |
|
T17 |
1 |
|
T44 |
1 |
| true |
1418 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
204 |
1 |
|
T1 |
12 |
|
T241 |
9 |
|
T76 |
1 |
| others[1] |
215 |
1 |
|
T1 |
10 |
|
T17 |
1 |
|
T20 |
1 |
| others[2] |
237 |
1 |
|
T1 |
4 |
|
T2 |
1 |
|
T70 |
1 |
| others[3] |
389 |
1 |
|
T1 |
13 |
|
T36 |
1 |
|
T118 |
1 |
| false |
140 |
1 |
|
T1 |
9 |
|
T8 |
1 |
|
T27 |
1 |
| true |
5725 |
1 |
|
T1 |
53 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T1 |
9 |
|
T44 |
1 |
|
T241 |
11 |
| others[1] |
210 |
1 |
|
T1 |
4 |
|
T37 |
1 |
|
T118 |
1 |
| others[2] |
236 |
1 |
|
T1 |
11 |
|
T71 |
1 |
|
T227 |
1 |
| others[3] |
380 |
1 |
|
T1 |
21 |
|
T8 |
1 |
|
T36 |
1 |
| false |
114 |
1 |
|
T1 |
7 |
|
T227 |
1 |
|
T41 |
1 |
| true |
5728 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T1 |
19 |
|
T4 |
1 |
|
T6 |
1 |
| others[1] |
1243 |
1 |
|
T1 |
16 |
|
T173 |
16 |
|
T241 |
15 |
| others[2] |
1275 |
1 |
|
T1 |
15 |
|
T192 |
1 |
|
T19 |
1 |
| others[3] |
2094 |
1 |
|
T1 |
45 |
|
T20 |
1 |
|
T36 |
1 |
| false |
642 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T227 |
1 |
| true |
426 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10 |
1 |
|
T164 |
1 |
|
T393 |
1 |
|
T394 |
1 |
| others[1] |
7 |
1 |
|
T74 |
1 |
|
T42 |
1 |
|
T111 |
1 |
| others[2] |
4 |
1 |
|
T240 |
1 |
|
T395 |
1 |
|
T396 |
1 |
| others[3] |
11 |
1 |
|
T54 |
1 |
|
T100 |
1 |
|
T397 |
1 |
| false |
2 |
1 |
|
T398 |
1 |
|
T399 |
1 |
|
- |
- |
| true |
58 |
1 |
|
T5 |
1 |
|
T154 |
1 |
|
T84 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2 |
1 |
|
T389 |
1 |
|
T400 |
1 |
|
- |
- |
| others[1] |
4 |
1 |
|
T31 |
1 |
|
T401 |
1 |
|
T402 |
1 |
| others[2] |
5 |
1 |
|
T403 |
1 |
|
T404 |
1 |
|
T405 |
1 |
| others[3] |
3 |
1 |
|
T260 |
1 |
|
T328 |
1 |
|
T406 |
1 |
| false |
7 |
1 |
|
T181 |
1 |
|
T407 |
1 |
|
T408 |
1 |
| true |
27 |
1 |
|
T21 |
1 |
|
T382 |
1 |
|
T180 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T328 |
1 |
|
T409 |
1 |
|
T410 |
1 |
| others[1] |
1 |
1 |
|
T389 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
4 |
1 |
|
T181 |
1 |
|
T411 |
1 |
|
T412 |
1 |
| others[3] |
6 |
1 |
|
T260 |
1 |
|
T180 |
1 |
|
T403 |
1 |
| false |
9 |
1 |
|
T21 |
1 |
|
T413 |
1 |
|
T414 |
1 |
| true |
23 |
1 |
|
T31 |
1 |
|
T382 |
1 |
|
T415 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |