Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10530 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T192 |
1 |
| others[1] |
825 |
1 |
|
T1 |
23 |
|
T117 |
1 |
|
T173 |
10 |
| others[2] |
814 |
1 |
|
T1 |
17 |
|
T6 |
1 |
|
T44 |
1 |
| others[3] |
1321 |
1 |
|
T1 |
37 |
|
T13 |
1 |
|
T25 |
1 |
| false |
405 |
1 |
|
T1 |
7 |
|
T19 |
1 |
|
T173 |
5 |
| true |
521 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2569 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T8 |
1 |
| others[1] |
2475 |
1 |
|
T1 |
8 |
|
T44 |
1 |
|
T37 |
1 |
| others[2] |
2385 |
1 |
|
T1 |
10 |
|
T35 |
1 |
|
T45 |
14 |
| others[3] |
4140 |
1 |
|
T1 |
25 |
|
T20 |
1 |
|
T192 |
1 |
| false |
1252 |
1 |
|
T1 |
4 |
|
T45 |
8 |
|
T72 |
1 |
| true |
1595 |
1 |
|
T1 |
44 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10010 |
1 |
|
T1 |
13 |
|
T17 |
1 |
|
T45 |
77 |
| others[1] |
277 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T6 |
1 |
| others[2] |
271 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T20 |
1 |
| others[3] |
432 |
1 |
|
T1 |
18 |
|
T25 |
1 |
|
T44 |
1 |
| false |
133 |
1 |
|
T1 |
4 |
|
T35 |
1 |
|
T41 |
1 |
| true |
3293 |
1 |
|
T1 |
48 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10249 |
1 |
|
T1 |
6 |
|
T26 |
1 |
|
T45 |
77 |
| others[1] |
455 |
1 |
|
T1 |
13 |
|
T19 |
1 |
|
T27 |
1 |
| others[2] |
476 |
1 |
|
T1 |
6 |
|
T74 |
1 |
|
T173 |
6 |
| others[3] |
762 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T5 |
1 |
| false |
238 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T20 |
1 |
| true |
2236 |
1 |
|
T1 |
52 |
|
T2 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9956 |
1 |
|
T1 |
13 |
|
T8 |
1 |
|
T35 |
1 |
| others[1] |
248 |
1 |
|
T1 |
10 |
|
T70 |
1 |
|
T239 |
1 |
| others[2] |
289 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T19 |
1 |
| others[3] |
458 |
1 |
|
T1 |
20 |
|
T2 |
1 |
|
T7 |
1 |
| false |
121 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T175 |
1 |
| true |
3344 |
1 |
|
T1 |
42 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T1 |
7 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
274 |
1 |
|
T1 |
8 |
|
T19 |
1 |
|
T35 |
1 |
| others[2] |
269 |
1 |
|
T1 |
10 |
|
T241 |
13 |
|
T212 |
1 |
| others[3] |
376 |
1 |
|
T1 |
9 |
|
T8 |
1 |
|
T192 |
1 |
| false |
134 |
1 |
|
T1 |
6 |
|
T241 |
8 |
|
T221 |
1 |
| true |
3401 |
1 |
|
T1 |
61 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10539 |
1 |
|
T1 |
18 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
824 |
1 |
|
T1 |
19 |
|
T192 |
1 |
|
T173 |
10 |
| others[2] |
824 |
1 |
|
T1 |
31 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
1334 |
1 |
|
T1 |
24 |
|
T13 |
1 |
|
T44 |
1 |
| false |
394 |
1 |
|
T1 |
9 |
|
T101 |
1 |
|
T173 |
8 |
| true |
501 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10478 |
1 |
|
T1 |
15 |
|
T19 |
1 |
|
T45 |
77 |
| others[1] |
841 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T13 |
1 |
| others[2] |
820 |
1 |
|
T1 |
21 |
|
T6 |
1 |
|
T173 |
17 |
| others[3] |
1332 |
1 |
|
T1 |
37 |
|
T2 |
1 |
|
T20 |
1 |
| false |
415 |
1 |
|
T1 |
13 |
|
T35 |
1 |
|
T88 |
1 |
| true |
499 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2528 |
1 |
|
T1 |
7 |
|
T36 |
1 |
|
T44 |
1 |
| others[1] |
2458 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T20 |
1 |
| others[2] |
2484 |
1 |
|
T1 |
11 |
|
T45 |
18 |
|
T72 |
1 |
| others[3] |
4039 |
1 |
|
T1 |
21 |
|
T192 |
1 |
|
T35 |
1 |
| false |
1307 |
1 |
|
T1 |
5 |
|
T45 |
8 |
|
T227 |
1 |
| true |
1569 |
1 |
|
T1 |
43 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9994 |
1 |
|
T1 |
10 |
|
T45 |
77 |
|
T227 |
1 |
| others[1] |
285 |
1 |
|
T1 |
16 |
|
T192 |
1 |
|
T238 |
1 |
| others[2] |
276 |
1 |
|
T1 |
4 |
|
T7 |
1 |
|
T26 |
1 |
| others[3] |
465 |
1 |
|
T1 |
13 |
|
T44 |
1 |
|
T70 |
1 |
| false |
145 |
1 |
|
T1 |
3 |
|
T241 |
5 |
|
T33 |
1 |
| true |
3220 |
1 |
|
T1 |
55 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10210 |
1 |
|
T1 |
11 |
|
T26 |
1 |
|
T35 |
1 |
| others[1] |
452 |
1 |
|
T1 |
5 |
|
T6 |
1 |
|
T20 |
1 |
| others[2] |
462 |
1 |
|
T1 |
10 |
|
T4 |
1 |
|
T17 |
1 |
| others[3] |
799 |
1 |
|
T1 |
15 |
|
T7 |
1 |
|
T8 |
1 |
| false |
268 |
1 |
|
T1 |
2 |
|
T19 |
1 |
|
T173 |
2 |
| true |
2194 |
1 |
|
T1 |
58 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9967 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T19 |
1 |
| others[1] |
281 |
1 |
|
T1 |
6 |
|
T35 |
1 |
|
T72 |
1 |
| others[2] |
243 |
1 |
|
T1 |
8 |
|
T241 |
8 |
|
T133 |
1 |
| others[3] |
464 |
1 |
|
T1 |
21 |
|
T26 |
1 |
|
T25 |
1 |
| false |
125 |
1 |
|
T1 |
3 |
|
T238 |
1 |
|
T73 |
1 |
| true |
3305 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9981 |
1 |
|
T1 |
12 |
|
T45 |
77 |
|
T71 |
1 |
| others[1] |
271 |
1 |
|
T1 |
11 |
|
T19 |
1 |
|
T239 |
1 |
| others[2] |
249 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T44 |
1 |
| others[3] |
451 |
1 |
|
T1 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| false |
144 |
1 |
|
T1 |
8 |
|
T192 |
1 |
|
T25 |
1 |
| true |
3289 |
1 |
|
T1 |
41 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10506 |
1 |
|
T1 |
22 |
|
T44 |
1 |
|
T45 |
77 |
| others[1] |
820 |
1 |
|
T1 |
23 |
|
T13 |
1 |
|
T20 |
1 |
| others[2] |
815 |
1 |
|
T1 |
10 |
|
T227 |
1 |
|
T116 |
1 |
| others[3] |
1357 |
1 |
|
T1 |
40 |
|
T4 |
1 |
|
T192 |
1 |
| false |
376 |
1 |
|
T1 |
6 |
|
T6 |
1 |
|
T117 |
1 |
| true |
511 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10532 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T6 |
1 |
| others[1] |
809 |
1 |
|
T1 |
17 |
|
T101 |
1 |
|
T27 |
1 |
| others[2] |
788 |
1 |
|
T1 |
21 |
|
T35 |
1 |
|
T22 |
1 |
| others[3] |
1340 |
1 |
|
T1 |
37 |
|
T4 |
1 |
|
T192 |
1 |
| false |
383 |
1 |
|
T1 |
11 |
|
T173 |
14 |
|
T241 |
8 |
| true |
533 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2496 |
1 |
|
T1 |
10 |
|
T45 |
13 |
|
T193 |
38 |
| others[1] |
2491 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T101 |
1 |
| others[2] |
2445 |
1 |
|
T1 |
10 |
|
T45 |
20 |
|
T391 |
1 |
| others[3] |
4157 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T8 |
1 |
| false |
1272 |
1 |
|
T1 |
6 |
|
T25 |
1 |
|
T19 |
1 |
| true |
1524 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9979 |
1 |
|
T1 |
12 |
|
T26 |
1 |
|
T36 |
1 |
| others[1] |
316 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T238 |
1 |
| others[2] |
290 |
1 |
|
T1 |
9 |
|
T20 |
1 |
|
T8 |
1 |
| others[3] |
427 |
1 |
|
T1 |
14 |
|
T2 |
1 |
|
T17 |
1 |
| false |
142 |
1 |
|
T1 |
6 |
|
T241 |
5 |
|
T179 |
1 |
| true |
3231 |
1 |
|
T1 |
46 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10234 |
1 |
|
T1 |
5 |
|
T75 |
1 |
|
T36 |
1 |
| others[1] |
493 |
1 |
|
T1 |
15 |
|
T2 |
1 |
|
T71 |
1 |
| others[2] |
466 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T35 |
1 |
| others[3] |
755 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T13 |
1 |
| false |
230 |
1 |
|
T1 |
3 |
|
T12 |
1 |
|
T20 |
1 |
| true |
2207 |
1 |
|
T1 |
51 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9986 |
1 |
|
T1 |
10 |
|
T25 |
1 |
|
T45 |
77 |
| others[1] |
295 |
1 |
|
T1 |
14 |
|
T35 |
1 |
|
T391 |
1 |
| others[2] |
270 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T239 |
1 |
| others[3] |
419 |
1 |
|
T1 |
18 |
|
T6 |
1 |
|
T27 |
1 |
| false |
119 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T227 |
1 |
| true |
3296 |
1 |
|
T1 |
42 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9979 |
1 |
|
T1 |
8 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
284 |
1 |
|
T1 |
10 |
|
T25 |
1 |
|
T72 |
1 |
| others[2] |
235 |
1 |
|
T1 |
6 |
|
T4 |
1 |
|
T241 |
7 |
| others[3] |
417 |
1 |
|
T1 |
14 |
|
T8 |
1 |
|
T192 |
1 |
| false |
125 |
1 |
|
T1 |
4 |
|
T391 |
1 |
|
T241 |
4 |
| true |
3345 |
1 |
|
T1 |
59 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10520 |
1 |
|
T1 |
20 |
|
T6 |
1 |
|
T45 |
77 |
| others[1] |
828 |
1 |
|
T1 |
24 |
|
T2 |
1 |
|
T19 |
1 |
| others[2] |
831 |
1 |
|
T1 |
14 |
|
T192 |
1 |
|
T173 |
12 |
| others[3] |
1293 |
1 |
|
T1 |
31 |
|
T4 |
1 |
|
T25 |
1 |
| false |
410 |
1 |
|
T1 |
12 |
|
T35 |
1 |
|
T173 |
3 |
| true |
503 |
1 |
|
T5 |
1 |
|
T17 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10464 |
1 |
|
T1 |
23 |
|
T35 |
1 |
|
T45 |
77 |
| others[1] |
807 |
1 |
|
T1 |
25 |
|
T44 |
1 |
|
T101 |
1 |
| others[2] |
827 |
1 |
|
T1 |
20 |
|
T192 |
1 |
|
T227 |
1 |
| others[3] |
1310 |
1 |
|
T1 |
26 |
|
T4 |
1 |
|
T6 |
1 |
| false |
450 |
1 |
|
T1 |
7 |
|
T25 |
1 |
|
T117 |
1 |
| true |
527 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2421 |
1 |
|
T1 |
14 |
|
T25 |
1 |
|
T19 |
1 |
| others[1] |
2441 |
1 |
|
T1 |
10 |
|
T35 |
1 |
|
T45 |
10 |
| others[2] |
2403 |
1 |
|
T1 |
9 |
|
T45 |
13 |
|
T70 |
1 |
| others[3] |
4229 |
1 |
|
T1 |
11 |
|
T6 |
1 |
|
T192 |
1 |
| false |
1339 |
1 |
|
T1 |
8 |
|
T20 |
1 |
|
T8 |
1 |
| true |
1552 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10001 |
1 |
|
T1 |
8 |
|
T20 |
1 |
|
T19 |
1 |
| others[1] |
256 |
1 |
|
T1 |
11 |
|
T25 |
1 |
|
T241 |
10 |
| others[2] |
284 |
1 |
|
T1 |
9 |
|
T17 |
1 |
|
T44 |
1 |
| others[3] |
471 |
1 |
|
T1 |
18 |
|
T192 |
1 |
|
T71 |
1 |
| false |
139 |
1 |
|
T1 |
5 |
|
T241 |
5 |
|
T179 |
1 |
| true |
3234 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10194 |
1 |
|
T1 |
11 |
|
T12 |
1 |
|
T8 |
1 |
| others[1] |
476 |
1 |
|
T1 |
8 |
|
T13 |
1 |
|
T55 |
1 |
| others[2] |
479 |
1 |
|
T1 |
9 |
|
T7 |
1 |
|
T227 |
1 |
| others[3] |
741 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T75 |
1 |
| false |
248 |
1 |
|
T1 |
5 |
|
T27 |
1 |
|
T227 |
1 |
| true |
2247 |
1 |
|
T1 |
54 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10012 |
1 |
|
T1 |
9 |
|
T7 |
1 |
|
T27 |
1 |
| others[1] |
274 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T192 |
1 |
| others[2] |
265 |
1 |
|
T1 |
11 |
|
T101 |
1 |
|
T70 |
1 |
| others[3] |
449 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T20 |
1 |
| false |
124 |
1 |
|
T1 |
1 |
|
T36 |
1 |
|
T175 |
1 |
| true |
3261 |
1 |
|
T1 |
54 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9963 |
1 |
|
T1 |
12 |
|
T4 |
1 |
|
T101 |
1 |
| others[1] |
252 |
1 |
|
T1 |
9 |
|
T37 |
1 |
|
T41 |
1 |
| others[2] |
267 |
1 |
|
T1 |
16 |
|
T70 |
1 |
|
T241 |
11 |
| others[3] |
377 |
1 |
|
T1 |
14 |
|
T36 |
1 |
|
T25 |
1 |
| false |
141 |
1 |
|
T1 |
3 |
|
T44 |
1 |
|
T241 |
6 |
| true |
3385 |
1 |
|
T1 |
47 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10483 |
1 |
|
T1 |
22 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
830 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T173 |
13 |
| others[2] |
810 |
1 |
|
T1 |
15 |
|
T44 |
1 |
|
T173 |
14 |
| others[3] |
1338 |
1 |
|
T1 |
25 |
|
T6 |
1 |
|
T20 |
1 |
| false |
421 |
1 |
|
T1 |
17 |
|
T173 |
8 |
|
T241 |
10 |
| true |
503 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10514 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T6 |
1 |
| others[1] |
840 |
1 |
|
T1 |
23 |
|
T19 |
1 |
|
T173 |
13 |
| others[2] |
757 |
1 |
|
T1 |
18 |
|
T27 |
1 |
|
T173 |
12 |
| others[3] |
1298 |
1 |
|
T1 |
31 |
|
T25 |
1 |
|
T44 |
1 |
| false |
445 |
1 |
|
T1 |
12 |
|
T192 |
1 |
|
T35 |
1 |
| true |
531 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2541 |
1 |
|
T1 |
8 |
|
T101 |
1 |
|
T45 |
18 |
| others[1] |
2367 |
1 |
|
T1 |
17 |
|
T20 |
1 |
|
T8 |
1 |
| others[2] |
2552 |
1 |
|
T1 |
8 |
|
T45 |
10 |
|
T70 |
1 |
| others[3] |
4061 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T25 |
1 |
| false |
1270 |
1 |
|
T1 |
6 |
|
T45 |
6 |
|
T391 |
1 |
| true |
1594 |
1 |
|
T1 |
48 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9974 |
1 |
|
T1 |
5 |
|
T45 |
77 |
|
T72 |
1 |
| others[1] |
268 |
1 |
|
T1 |
9 |
|
T118 |
1 |
|
T241 |
8 |
| others[2] |
290 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T391 |
1 |
| others[3] |
457 |
1 |
|
T1 |
17 |
|
T8 |
1 |
|
T192 |
1 |
| false |
161 |
1 |
|
T1 |
2 |
|
T241 |
5 |
|
T32 |
1 |
| true |
3235 |
1 |
|
T1 |
60 |
|
T4 |
1 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |