Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10230 |
1 |
|
T1 |
6 |
|
T5 |
1 |
|
T12 |
1 |
| others[1] |
444 |
1 |
|
T1 |
7 |
|
T4 |
1 |
|
T227 |
1 |
| others[2] |
441 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T101 |
1 |
| others[3] |
796 |
1 |
|
T1 |
16 |
|
T74 |
1 |
|
T25 |
1 |
| false |
232 |
1 |
|
T1 |
2 |
|
T20 |
1 |
|
T54 |
1 |
| true |
2242 |
1 |
|
T1 |
58 |
|
T6 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T1 |
12 |
|
T7 |
1 |
|
T19 |
1 |
| others[1] |
270 |
1 |
|
T1 |
14 |
|
T26 |
1 |
|
T227 |
1 |
| others[2] |
261 |
1 |
|
T1 |
6 |
|
T2 |
1 |
|
T72 |
1 |
| others[3] |
458 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T17 |
1 |
| false |
141 |
1 |
|
T1 |
8 |
|
T192 |
1 |
|
T117 |
1 |
| true |
3293 |
1 |
|
T1 |
45 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9969 |
1 |
|
T1 |
9 |
|
T4 |
1 |
|
T45 |
77 |
| others[1] |
232 |
1 |
|
T1 |
7 |
|
T71 |
1 |
|
T227 |
1 |
| others[2] |
254 |
1 |
|
T1 |
7 |
|
T241 |
15 |
|
T221 |
1 |
| others[3] |
428 |
1 |
|
T1 |
22 |
|
T35 |
1 |
|
T241 |
14 |
| false |
129 |
1 |
|
T1 |
7 |
|
T6 |
1 |
|
T20 |
1 |
| true |
3373 |
1 |
|
T1 |
49 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10558 |
1 |
|
T1 |
23 |
|
T44 |
1 |
|
T45 |
77 |
| others[1] |
796 |
1 |
|
T1 |
22 |
|
T20 |
1 |
|
T88 |
1 |
| others[2] |
813 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T6 |
1 |
| others[3] |
1272 |
1 |
|
T1 |
32 |
|
T192 |
1 |
|
T19 |
1 |
| false |
426 |
1 |
|
T1 |
8 |
|
T25 |
1 |
|
T173 |
6 |
| true |
520 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10512 |
1 |
|
T1 |
16 |
|
T192 |
1 |
|
T25 |
1 |
| others[1] |
787 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T6 |
1 |
| others[2] |
810 |
1 |
|
T1 |
23 |
|
T117 |
1 |
|
T173 |
13 |
| others[3] |
1318 |
1 |
|
T1 |
31 |
|
T116 |
1 |
|
T22 |
1 |
| false |
442 |
1 |
|
T1 |
13 |
|
T19 |
1 |
|
T35 |
1 |
| true |
516 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2468 |
1 |
|
T1 |
17 |
|
T44 |
1 |
|
T19 |
1 |
| others[1] |
2518 |
1 |
|
T1 |
15 |
|
T6 |
1 |
|
T45 |
16 |
| others[2] |
2473 |
1 |
|
T1 |
9 |
|
T8 |
1 |
|
T192 |
1 |
| others[3] |
4112 |
1 |
|
T1 |
16 |
|
T20 |
1 |
|
T36 |
1 |
| false |
1282 |
1 |
|
T1 |
6 |
|
T101 |
1 |
|
T35 |
1 |
| true |
1532 |
1 |
|
T1 |
38 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10006 |
1 |
|
T1 |
9 |
|
T45 |
77 |
|
T70 |
1 |
| others[1] |
246 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T241 |
10 |
| others[2] |
300 |
1 |
|
T1 |
13 |
|
T26 |
1 |
|
T192 |
1 |
| others[3] |
456 |
1 |
|
T1 |
13 |
|
T36 |
1 |
|
T37 |
1 |
| false |
138 |
1 |
|
T1 |
5 |
|
T25 |
1 |
|
T241 |
4 |
| true |
3239 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10217 |
1 |
|
T1 |
8 |
|
T2 |
1 |
|
T4 |
1 |
| others[1] |
456 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T136 |
1 |
| others[2] |
466 |
1 |
|
T1 |
9 |
|
T6 |
1 |
|
T12 |
1 |
| others[3] |
795 |
1 |
|
T1 |
20 |
|
T13 |
1 |
|
T55 |
1 |
| false |
256 |
1 |
|
T1 |
4 |
|
T75 |
1 |
|
T173 |
3 |
| true |
2195 |
1 |
|
T1 |
50 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9981 |
1 |
|
T1 |
12 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
252 |
1 |
|
T1 |
7 |
|
T2 |
1 |
|
T36 |
1 |
| others[2] |
264 |
1 |
|
T1 |
11 |
|
T73 |
1 |
|
T241 |
14 |
| others[3] |
464 |
1 |
|
T1 |
18 |
|
T4 |
1 |
|
T6 |
1 |
| false |
133 |
1 |
|
T1 |
6 |
|
T241 |
3 |
|
T179 |
1 |
| true |
3291 |
1 |
|
T1 |
47 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9976 |
1 |
|
T1 |
10 |
|
T45 |
77 |
|
T391 |
1 |
| others[1] |
271 |
1 |
|
T1 |
5 |
|
T19 |
1 |
|
T241 |
11 |
| others[2] |
249 |
1 |
|
T1 |
17 |
|
T36 |
1 |
|
T241 |
10 |
| others[3] |
378 |
1 |
|
T1 |
10 |
|
T20 |
1 |
|
T25 |
1 |
| false |
115 |
1 |
|
T1 |
2 |
|
T4 |
1 |
|
T239 |
1 |
| true |
3396 |
1 |
|
T1 |
57 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10576 |
1 |
|
T1 |
15 |
|
T7 |
1 |
|
T101 |
1 |
| others[1] |
767 |
1 |
|
T1 |
18 |
|
T6 |
1 |
|
T36 |
1 |
| others[2] |
817 |
1 |
|
T1 |
23 |
|
T74 |
1 |
|
T239 |
1 |
| others[3] |
1311 |
1 |
|
T1 |
35 |
|
T4 |
1 |
|
T20 |
1 |
| false |
402 |
1 |
|
T1 |
10 |
|
T192 |
1 |
|
T173 |
10 |
| true |
512 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10540 |
1 |
|
T1 |
16 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
796 |
1 |
|
T1 |
22 |
|
T4 |
1 |
|
T192 |
1 |
| others[2] |
762 |
1 |
|
T1 |
14 |
|
T44 |
1 |
|
T19 |
1 |
| others[3] |
1350 |
1 |
|
T1 |
39 |
|
T6 |
1 |
|
T25 |
1 |
| false |
422 |
1 |
|
T1 |
10 |
|
T22 |
1 |
|
T173 |
12 |
| true |
515 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2413 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T20 |
1 |
| others[1] |
2463 |
1 |
|
T1 |
9 |
|
T44 |
1 |
|
T19 |
1 |
| others[2] |
2457 |
1 |
|
T1 |
9 |
|
T45 |
16 |
|
T227 |
1 |
| others[3] |
4112 |
1 |
|
T1 |
10 |
|
T6 |
1 |
|
T192 |
1 |
| false |
1324 |
1 |
|
T1 |
7 |
|
T25 |
1 |
|
T35 |
1 |
| true |
1616 |
1 |
|
T1 |
50 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10013 |
1 |
|
T1 |
9 |
|
T2 |
1 |
|
T192 |
1 |
| others[1] |
257 |
1 |
|
T1 |
12 |
|
T227 |
1 |
|
T116 |
1 |
| others[2] |
281 |
1 |
|
T1 |
11 |
|
T4 |
1 |
|
T19 |
1 |
| others[3] |
444 |
1 |
|
T1 |
12 |
|
T6 |
1 |
|
T227 |
1 |
| false |
154 |
1 |
|
T1 |
7 |
|
T241 |
3 |
|
T132 |
1 |
| true |
3236 |
1 |
|
T1 |
50 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10156 |
1 |
|
T1 |
15 |
|
T36 |
1 |
|
T25 |
1 |
| others[1] |
494 |
1 |
|
T1 |
10 |
|
T26 |
1 |
|
T137 |
1 |
| others[2] |
491 |
1 |
|
T1 |
11 |
|
T2 |
1 |
|
T173 |
8 |
| others[3] |
766 |
1 |
|
T1 |
13 |
|
T13 |
1 |
|
T20 |
1 |
| false |
246 |
1 |
|
T1 |
5 |
|
T73 |
1 |
|
T241 |
9 |
| true |
2232 |
1 |
|
T1 |
47 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9978 |
1 |
|
T1 |
9 |
|
T192 |
1 |
|
T45 |
77 |
| others[1] |
278 |
1 |
|
T1 |
14 |
|
T6 |
1 |
|
T17 |
1 |
| others[2] |
258 |
1 |
|
T1 |
10 |
|
T7 |
1 |
|
T25 |
1 |
| others[3] |
422 |
1 |
|
T1 |
13 |
|
T2 |
1 |
|
T4 |
1 |
| false |
131 |
1 |
|
T1 |
3 |
|
T73 |
1 |
|
T118 |
1 |
| true |
3318 |
1 |
|
T1 |
52 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T1 |
17 |
|
T19 |
1 |
|
T37 |
1 |
| others[1] |
239 |
1 |
|
T1 |
6 |
|
T72 |
1 |
|
T227 |
1 |
| others[2] |
254 |
1 |
|
T1 |
13 |
|
T4 |
1 |
|
T20 |
1 |
| others[3] |
405 |
1 |
|
T1 |
18 |
|
T227 |
1 |
|
T73 |
1 |
| false |
126 |
1 |
|
T1 |
3 |
|
T238 |
1 |
|
T241 |
7 |
| true |
3372 |
1 |
|
T1 |
44 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10556 |
1 |
|
T1 |
24 |
|
T4 |
1 |
|
T19 |
1 |
| others[1] |
790 |
1 |
|
T1 |
16 |
|
T192 |
1 |
|
T25 |
1 |
| others[2] |
803 |
1 |
|
T1 |
26 |
|
T6 |
1 |
|
T35 |
1 |
| others[3] |
1328 |
1 |
|
T1 |
30 |
|
T7 |
1 |
|
T20 |
1 |
| false |
400 |
1 |
|
T1 |
5 |
|
T173 |
6 |
|
T241 |
9 |
| true |
508 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10483 |
1 |
|
T1 |
17 |
|
T192 |
1 |
|
T35 |
1 |
| others[1] |
790 |
1 |
|
T1 |
21 |
|
T101 |
1 |
|
T227 |
1 |
| others[2] |
800 |
1 |
|
T1 |
21 |
|
T13 |
1 |
|
T25 |
1 |
| others[3] |
1375 |
1 |
|
T1 |
34 |
|
T4 |
1 |
|
T6 |
1 |
| false |
412 |
1 |
|
T1 |
8 |
|
T173 |
13 |
|
T241 |
12 |
| true |
525 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2450 |
1 |
|
T1 |
10 |
|
T25 |
1 |
|
T45 |
17 |
| others[1] |
2483 |
1 |
|
T1 |
15 |
|
T8 |
1 |
|
T36 |
1 |
| others[2] |
2478 |
1 |
|
T1 |
3 |
|
T6 |
1 |
|
T192 |
1 |
| others[3] |
4179 |
1 |
|
T1 |
14 |
|
T20 |
1 |
|
T44 |
1 |
| false |
1238 |
1 |
|
T1 |
8 |
|
T45 |
9 |
|
T239 |
1 |
| true |
1557 |
1 |
|
T1 |
51 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9989 |
1 |
|
T1 |
11 |
|
T45 |
77 |
|
T70 |
1 |
| others[1] |
279 |
1 |
|
T1 |
8 |
|
T17 |
1 |
|
T192 |
1 |
| others[2] |
281 |
1 |
|
T1 |
5 |
|
T2 |
1 |
|
T116 |
1 |
| others[3] |
455 |
1 |
|
T1 |
17 |
|
T4 |
1 |
|
T36 |
1 |
| false |
155 |
1 |
|
T1 |
4 |
|
T6 |
1 |
|
T227 |
1 |
| true |
3226 |
1 |
|
T1 |
56 |
|
T5 |
1 |
|
T12 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10183 |
1 |
|
T1 |
12 |
|
T7 |
1 |
|
T192 |
1 |
| others[1] |
450 |
1 |
|
T1 |
8 |
|
T4 |
1 |
|
T136 |
1 |
| others[2] |
472 |
1 |
|
T1 |
9 |
|
T26 |
1 |
|
T36 |
1 |
| others[3] |
801 |
1 |
|
T1 |
12 |
|
T2 |
1 |
|
T17 |
1 |
| false |
265 |
1 |
|
T1 |
4 |
|
T20 |
1 |
|
T239 |
1 |
| true |
2214 |
1 |
|
T1 |
56 |
|
T5 |
1 |
|
T6 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9979 |
1 |
|
T1 |
8 |
|
T26 |
1 |
|
T45 |
77 |
| others[1] |
294 |
1 |
|
T1 |
6 |
|
T44 |
1 |
|
T239 |
1 |
| others[2] |
261 |
1 |
|
T1 |
10 |
|
T8 |
1 |
|
T35 |
1 |
| others[3] |
454 |
1 |
|
T1 |
16 |
|
T4 |
1 |
|
T19 |
1 |
| false |
135 |
1 |
|
T1 |
7 |
|
T241 |
6 |
|
T28 |
1 |
| true |
3262 |
1 |
|
T1 |
54 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9962 |
1 |
|
T1 |
9 |
|
T25 |
1 |
|
T45 |
77 |
| others[1] |
256 |
1 |
|
T1 |
15 |
|
T241 |
9 |
|
T221 |
1 |
| others[2] |
228 |
1 |
|
T1 |
8 |
|
T6 |
1 |
|
T36 |
1 |
| others[3] |
423 |
1 |
|
T1 |
15 |
|
T4 |
1 |
|
T44 |
1 |
| false |
135 |
1 |
|
T1 |
10 |
|
T241 |
3 |
|
T82 |
7 |
| true |
3381 |
1 |
|
T1 |
44 |
|
T2 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10500 |
1 |
|
T1 |
18 |
|
T45 |
77 |
|
T193 |
183 |
| others[1] |
842 |
1 |
|
T1 |
20 |
|
T25 |
1 |
|
T44 |
1 |
| others[2] |
784 |
1 |
|
T1 |
18 |
|
T117 |
1 |
|
T173 |
8 |
| others[3] |
1352 |
1 |
|
T1 |
35 |
|
T4 |
1 |
|
T6 |
1 |
| false |
407 |
1 |
|
T1 |
10 |
|
T192 |
1 |
|
T27 |
1 |
| true |
500 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T17 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |