Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	226882	1		T1	100		T2	28		T4	160
auto[FlashEraseBank]	253435	1		T1	825		T2	41		T4	40

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	266224	1		T1	446		T2	31		T4	86
auto[FlashOpProgram]	193933	1		T1	422		T2	38		T4	81
auto[FlashOpErase]	16160	1		T1	57		T4	33		T17	35
auto[FlashOpInvalid]	4000	1		T226	200		T307	200		T115	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	266224	1		T1	446		T2	31		T4	86
op[FlashOpProgram]	193933	1		T1	422		T2	38		T4	81
op[FlashOpErase]	16160	1		T1	57		T4	33		T17	35
read_erase_read	755	1		T1	3		T4	11		T17	21
read_prog_read	1224	1		T1	3		T2	12		T4	14

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	339490	1		T1	90		T2	62		T4	198
auto[FlashPartInfo]	137120	1		T1	835		T2	6		T4	2
auto[FlashPartInfo1]	869	1		T8	2		T19	1		T37	2
auto[FlashPartInfo2]	2838	1		T2	1		T17	1		T8	12

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	203273	1		T1	28		T2	24		T4	84
auto[FlashPartData]	auto[FlashOpProgram]	128537	1		T1	33		T2	38		T4	81
auto[FlashPartData]	auto[FlashOpErase]	3760	1		T1	29		T4	33		T17	15
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T226	198		T307	200		T115	200
auto[FlashPartInfo]	auto[FlashOpRead]	60526	1		T1	418		T2	6		T4	2
auto[FlashPartInfo]	auto[FlashOpProgram]	64176	1		T1	389		T21	320		T31	256
auto[FlashPartInfo]	auto[FlashOpErase]	12348	1		T1	28		T17	20		T21	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T226	2		T417	4		T127	4
auto[FlashPartInfo1]	auto[FlashOpRead]	701	1		T8	2		T19	1		T37	2
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T83	1		T240	1		T94	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T418	1		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	2	1		T418	2		-	-		-	-
auto[FlashPartInfo2]	auto[FlashOpRead]	1724	1		T2	1		T17	1		T8	8
auto[FlashPartInfo2]	auto[FlashOpProgram]	1055	1		T8	4		T25	32		T101	7
auto[FlashPartInfo2]	auto[FlashOpErase]	51	1		T116	21		T95	1		T352	8
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T127	2		T419	2		T420	2