Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.48	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	4	28	87.50

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	4	28	87.50	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31006	1		T1	8		T2	42		T4	20
auto[1]	16	1		T351	1		T292	2		T352	5
auto[2]	75	1		T228	8		T56	4		T353	3
auto[3]	218	1		T28	1		T38	1		T354	2

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7857	1		T1	2		T2	12		T4	5
evic_idx[1]	7849	1		T1	2		T2	10		T4	5
evic_idx[2]	7812	1		T1	2		T2	10		T4	5
evic_idx[3]	7797	1		T1	2		T2	10		T4	5

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30205	1		T45	232		T193	532		T174	796
evic_op[2]	492	1		T2	42		T31	4		T28	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	4	28	87.50	4

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
*	[evic_op[1]]	[auto[2]]	--	--	4

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7511	1		T45	58		T193	133		T174	199
evic_idx[0]	evic_op[1]	auto[1]	1	1		T352	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	56	1		T355	19		T356	26		T357	7
evic_idx[0]	evic_op[2]	auto[0]	99	1		T2	12		T31	1		T135	1
evic_idx[0]	evic_op[2]	auto[1]	3	1		T351	1		T188	1		T358	1
evic_idx[0]	evic_op[2]	auto[2]	15	1		T228	5		T353	2		T359	1
evic_idx[0]	evic_op[2]	auto[3]	17	1		T28	1		T354	1		T119	1
evic_idx[1]	evic_op[1]	auto[0]	7508	1		T45	58		T193	133		T174	199
evic_idx[1]	evic_op[1]	auto[1]	2	1		T352	2		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	48	1		T355	11		T356	22		T357	13
evic_idx[1]	evic_op[2]	auto[0]	108	1		T2	10		T31	1		T233	9
evic_idx[1]	evic_op[2]	auto[1]	1	1		T292	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	10	1		T228	3		T360	1		T361	6
evic_idx[1]	evic_op[2]	auto[3]	17	1		T39	1		T362	1		T40	1
evic_idx[2]	evic_op[1]	auto[0]	7509	1		T45	58		T193	133		T174	199
evic_idx[2]	evic_op[1]	auto[1]	1	1		T352	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	36	1		T355	12		T356	13		T357	8
evic_idx[2]	evic_op[2]	auto[0]	89	1		T2	10		T31	1		T233	9
evic_idx[2]	evic_op[2]	auto[1]	5	1		T292	1		T188	2		T363	1
evic_idx[2]	evic_op[2]	auto[2]	10	1		T364	1		T360	1		T361	7
evic_idx[2]	evic_op[2]	auto[3]	8	1		T38	1		T365	1		T128	1
evic_idx[3]	evic_op[1]	auto[0]	7509	1		T45	58		T193	133		T174	199
evic_idx[3]	evic_op[1]	auto[1]	1	1		T352	1		-	-		-	-
evic_idx[3]	evic_op[1]	auto[3]	23	1		T355	12		T356	6		T357	4
evic_idx[3]	evic_op[2]	auto[0]	87	1		T2	10		T31	1		T233	9
evic_idx[3]	evic_op[2]	auto[1]	2	1		T188	2		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	8	1		T353	1		T360	3		T361	4
evic_idx[3]	evic_op[2]	auto[3]	13	1		T354	1		T39	1		T366	1