Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

---

Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	21204	1		T7	1288		T323	8102		T345	9031
rd_lvl[2]	36894	1		T6	5192		T7	1687		T323	3946
rd_lvl[3]	16768	1		T6	328		T7	604		T293	1296
rd_lvl[4]	31130	1		T7	1261		T293	3266		T294	3039
rd_lvl[5]	20658	1		T7	497		T293	356		T294	334
rd_lvl[6]	16700	1		T7	701		T293	119		T294	58
rd_lvl[7]	10882	1		T7	285		T293	114		T294	5
rd_lvl[8]	17859	1		T7	461		T293	9		T346	587
rd_lvl[9]	5856	1		T7	705		T299	24		T347	625
rd_lvl[10]	3539	1		T7	124		T32	491		T293	1
rd_lvl[11]	5906	1		T7	1259		T32	342		T348	664
rd_lvl[12]	5099	1		T7	2		T348	332		T349	507
rd_lvl[13]	5309	1		T7	1		T35	568		T32	1
rd_lvl[14]	6984	1		T7	89		T35	494		T348	74
rd_lvl[15]	6584	1		T33	594		T34	582		T350	157