Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	311020	1		T1	2		T2	1		T3	1
all_pins[1]	311020	1		T1	2		T2	1		T3	1
all_pins[2]	311020	1		T1	2		T2	1		T3	1
all_pins[3]	311020	1		T1	2		T2	1		T3	1
all_pins[4]	311020	1		T1	2		T2	1		T3	1
all_pins[5]	311020	1		T1	2		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1545924	1		T1	12		T2	6		T3	6
values[0x1]	320196	1		T6	6251		T7	10163		T25	941
transitions[0x0=>0x1]	287415	1		T6	5848		T7	8974		T25	941
transitions[0x1=>0x0]	287395	1		T6	5848		T7	8974		T25	941

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	310843	1		T1	2		T2	1		T3	1
all_pins[0]	values[0x1]	177	1		T273	2		T274	5		T338	5
all_pins[0]	transitions[0x0=>0x1]	87	1		T273	1		T274	1		T340	1
all_pins[0]	transitions[0x1=>0x0]	72	1		T340	4		T341	3		T342	1
all_pins[1]	values[0x0]	310858	1		T1	2		T2	1		T3	1
all_pins[1]	values[0x1]	162	1		T273	1		T274	4		T338	5
all_pins[1]	transitions[0x0=>0x1]	141	1		T273	1		T274	2		T338	5
all_pins[1]	transitions[0x1=>0x0]	2488	1		T33	377		T34	296		T350	456
all_pins[2]	values[0x0]	308511	1		T1	2		T2	1		T3	1
all_pins[2]	values[0x1]	2509	1		T33	377		T34	296		T350	456
all_pins[2]	transitions[0x0=>0x1]	42	1		T274	2		T340	1		T339	1
all_pins[2]	transitions[0x1=>0x0]	212049	1		T6	5520		T7	8964		T35	1062
all_pins[3]	values[0x0]	96504	1		T1	2		T2	1		T3	1
all_pins[3]	values[0x1]	214516	1		T6	5520		T7	8964		T35	1062
all_pins[3]	transitions[0x0=>0x1]	184365	1		T6	5117		T7	7775		T35	1062
all_pins[3]	transitions[0x1=>0x0]	72621	1		T6	328		T7	10		T25	941
all_pins[4]	values[0x0]	208248	1		T1	2		T2	1		T3	1
all_pins[4]	values[0x1]	102772	1		T6	731		T7	1199		T25	941
all_pins[4]	transitions[0x0=>0x1]	102757	1		T6	731		T7	1199		T25	941
all_pins[4]	transitions[0x1=>0x0]	45	1		T273	2		T274	2		T338	2
all_pins[5]	values[0x0]	310960	1		T1	2		T2	1		T3	1
all_pins[5]	values[0x1]	60	1		T273	2		T274	2		T338	2
all_pins[5]	transitions[0x0=>0x1]	23	1		T341	2		T343	1		T371	1
all_pins[5]	transitions[0x1=>0x0]	120	1		T273	1		T274	2		T338	2