| T1080 |
/workspace/coverage/default/34.flash_ctrl_alert_test.1272341045 |
|
|
Mar 28 02:41:43 PM PDT 24 |
Mar 28 02:41:57 PM PDT 24 |
21540100 ps |
| T1081 |
/workspace/coverage/default/12.flash_ctrl_sec_info_access.2034940751 |
|
|
Mar 28 02:37:39 PM PDT 24 |
Mar 28 02:38:46 PM PDT 24 |
1849974600 ps |
| T1082 |
/workspace/coverage/default/7.flash_ctrl_ro_derr.2338677026 |
|
|
Mar 28 02:35:15 PM PDT 24 |
Mar 28 02:37:44 PM PDT 24 |
1289366100 ps |
| T1083 |
/workspace/coverage/default/16.flash_ctrl_hw_read_seed_err.3939683168 |
|
|
Mar 28 02:38:52 PM PDT 24 |
Mar 28 02:39:06 PM PDT 24 |
15754500 ps |
| T1084 |
/workspace/coverage/default/20.flash_ctrl_prog_reset.940611360 |
|
|
Mar 28 02:39:41 PM PDT 24 |
Mar 28 02:39:55 PM PDT 24 |
34876400 ps |
| T1085 |
/workspace/coverage/default/1.flash_ctrl_phy_arb.2143788954 |
|
|
Mar 28 02:31:24 PM PDT 24 |
Mar 28 02:32:34 PM PDT 24 |
26943200 ps |
| T53 |
/workspace/coverage/default/9.flash_ctrl_fetch_code.68102224 |
|
|
Mar 28 02:36:08 PM PDT 24 |
Mar 28 02:36:37 PM PDT 24 |
2505307300 ps |
| T1086 |
/workspace/coverage/default/9.flash_ctrl_rw_evict_all_en.1727153767 |
|
|
Mar 28 02:36:09 PM PDT 24 |
Mar 28 02:36:40 PM PDT 24 |
78212900 ps |
| T1087 |
/workspace/coverage/default/46.flash_ctrl_smoke.207861458 |
|
|
Mar 28 02:42:36 PM PDT 24 |
Mar 28 02:43:30 PM PDT 24 |
24435700 ps |
| T1088 |
/workspace/coverage/default/10.flash_ctrl_smoke.4027034852 |
|
|
Mar 28 02:36:26 PM PDT 24 |
Mar 28 02:38:57 PM PDT 24 |
840990600 ps |
| T1089 |
/workspace/coverage/default/60.flash_ctrl_otp_reset.805611710 |
|
|
Mar 28 02:42:56 PM PDT 24 |
Mar 28 02:44:48 PM PDT 24 |
138804000 ps |
| T1090 |
/workspace/coverage/default/3.flash_ctrl_stress_all.623789115 |
|
|
Mar 28 02:33:20 PM PDT 24 |
Mar 28 03:00:42 PM PDT 24 |
819575700 ps |
| T1091 |
/workspace/coverage/default/49.flash_ctrl_connect.2515776592 |
|
|
Mar 28 02:42:56 PM PDT 24 |
Mar 28 02:43:10 PM PDT 24 |
25760100 ps |
| T1092 |
/workspace/coverage/default/3.flash_ctrl_ro.1281929957 |
|
|
Mar 28 02:33:06 PM PDT 24 |
Mar 28 02:34:40 PM PDT 24 |
459370700 ps |
| T201 |
/workspace/coverage/default/2.flash_ctrl_sec_cm.3692568071 |
|
|
Mar 28 02:32:14 PM PDT 24 |
Mar 28 03:50:55 PM PDT 24 |
1977653500 ps |
| T1093 |
/workspace/coverage/default/79.flash_ctrl_connect.2349737303 |
|
|
Mar 28 02:43:21 PM PDT 24 |
Mar 28 02:43:37 PM PDT 24 |
21201100 ps |
| T1094 |
/workspace/coverage/default/2.flash_ctrl_rw.652426102 |
|
|
Mar 28 02:31:57 PM PDT 24 |
Mar 28 02:41:31 PM PDT 24 |
2624621400 ps |
| T186 |
/workspace/coverage/default/55.flash_ctrl_otp_reset.3213646358 |
|
|
Mar 28 02:42:58 PM PDT 24 |
Mar 28 02:45:09 PM PDT 24 |
41462500 ps |
| T1095 |
/workspace/coverage/default/11.flash_ctrl_hw_rma_reset.2734410569 |
|
|
Mar 28 02:36:44 PM PDT 24 |
Mar 28 02:51:29 PM PDT 24 |
210240929800 ps |
| T1096 |
/workspace/coverage/default/8.flash_ctrl_intr_wr_slow_flash.3955279855 |
|
|
Mar 28 02:35:51 PM PDT 24 |
Mar 28 02:41:28 PM PDT 24 |
90003121600 ps |
| T1097 |
/workspace/coverage/default/27.flash_ctrl_prog_reset.3184407352 |
|
|
Mar 28 02:40:50 PM PDT 24 |
Mar 28 02:41:03 PM PDT 24 |
21593200 ps |
| T1098 |
/workspace/coverage/default/47.flash_ctrl_alert_test.2731002807 |
|
|
Mar 28 02:42:38 PM PDT 24 |
Mar 28 02:42:52 PM PDT 24 |
33813000 ps |
| T1099 |
/workspace/coverage/default/38.flash_ctrl_alert_test.3538097050 |
|
|
Mar 28 02:42:01 PM PDT 24 |
Mar 28 02:42:15 PM PDT 24 |
101390900 ps |
| T1100 |
/workspace/coverage/default/2.flash_ctrl_stress_all.3761864843 |
|
|
Mar 28 02:32:15 PM PDT 24 |
Mar 28 02:55:26 PM PDT 24 |
579928800 ps |
| T1101 |
/workspace/coverage/default/29.flash_ctrl_otp_reset.2687320424 |
|
|
Mar 28 02:40:45 PM PDT 24 |
Mar 28 02:42:33 PM PDT 24 |
41661000 ps |
| T1102 |
/workspace/coverage/default/9.flash_ctrl_intr_rd.2778204984 |
|
|
Mar 28 02:36:08 PM PDT 24 |
Mar 28 02:38:34 PM PDT 24 |
1918297700 ps |
| T1103 |
/workspace/coverage/default/15.flash_ctrl_intr_rd_slow_flash.314017958 |
|
|
Mar 28 02:38:13 PM PDT 24 |
Mar 28 02:41:38 PM PDT 24 |
8826678700 ps |
| T1104 |
/workspace/coverage/default/23.flash_ctrl_sec_info_access.2414650323 |
|
|
Mar 28 02:40:11 PM PDT 24 |
Mar 28 02:41:25 PM PDT 24 |
1920688300 ps |
| T1105 |
/workspace/coverage/default/16.flash_ctrl_phy_arb.1628044359 |
|
|
Mar 28 02:38:28 PM PDT 24 |
Mar 28 02:42:20 PM PDT 24 |
243488200 ps |
| T1106 |
/workspace/coverage/default/4.flash_ctrl_wo.354734962 |
|
|
Mar 28 02:33:38 PM PDT 24 |
Mar 28 02:37:18 PM PDT 24 |
9328740100 ps |
| T1107 |
/workspace/coverage/default/3.flash_ctrl_full_mem_access.630841156 |
|
|
Mar 28 02:33:02 PM PDT 24 |
Mar 28 03:15:24 PM PDT 24 |
88201780900 ps |
| T1108 |
/workspace/coverage/default/22.flash_ctrl_hw_sec_otp.890257530 |
|
|
Mar 28 02:39:58 PM PDT 24 |
Mar 28 02:42:04 PM PDT 24 |
2796816700 ps |
| T1109 |
/workspace/coverage/default/18.flash_ctrl_invalid_op.633747210 |
|
|
Mar 28 02:39:20 PM PDT 24 |
Mar 28 02:40:40 PM PDT 24 |
6516704100 ps |
| T265 |
/workspace/coverage/default/2.flash_ctrl_integrity.2857973817 |
|
|
Mar 28 02:31:59 PM PDT 24 |
Mar 28 02:40:47 PM PDT 24 |
5905266600 ps |
| T1110 |
/workspace/coverage/default/18.flash_ctrl_sec_info_access.4127673252 |
|
|
Mar 28 02:39:20 PM PDT 24 |
Mar 28 02:40:24 PM PDT 24 |
1336914700 ps |
| T1111 |
/workspace/coverage/default/19.flash_ctrl_rw.2100380237 |
|
|
Mar 28 02:39:38 PM PDT 24 |
Mar 28 02:48:07 PM PDT 24 |
22936775100 ps |
| T1112 |
/workspace/coverage/default/39.flash_ctrl_otp_reset.3752845378 |
|
|
Mar 28 02:42:04 PM PDT 24 |
Mar 28 02:44:16 PM PDT 24 |
38185000 ps |
| T1113 |
/workspace/coverage/default/0.flash_ctrl_rw.3265558989 |
|
|
Mar 28 02:31:16 PM PDT 24 |
Mar 28 02:40:13 PM PDT 24 |
15989711500 ps |
| T1114 |
/workspace/coverage/default/3.flash_ctrl_error_prog_win.2760408625 |
|
|
Mar 28 02:33:05 PM PDT 24 |
Mar 28 02:47:46 PM PDT 24 |
600324200 ps |
| T11 |
/workspace/coverage/default/0.flash_ctrl_wr_intg.165617877 |
|
|
Mar 28 02:31:31 PM PDT 24 |
Mar 28 02:31:45 PM PDT 24 |
166804300 ps |
| T1115 |
/workspace/coverage/default/1.flash_ctrl_sec_info_access.2571008395 |
|
|
Mar 28 02:31:45 PM PDT 24 |
Mar 28 02:32:51 PM PDT 24 |
2070866000 ps |
| T1116 |
/workspace/coverage/default/6.flash_ctrl_otp_reset.206316679 |
|
|
Mar 28 02:34:44 PM PDT 24 |
Mar 28 02:36:57 PM PDT 24 |
128307300 ps |
| T1117 |
/workspace/coverage/default/3.flash_ctrl_error_prog_type.3903181481 |
|
|
Mar 28 02:33:02 PM PDT 24 |
Mar 28 03:07:27 PM PDT 24 |
746128900 ps |
| T1118 |
/workspace/coverage/default/29.flash_ctrl_smoke.2647649194 |
|
|
Mar 28 02:40:46 PM PDT 24 |
Mar 28 02:42:27 PM PDT 24 |
116874600 ps |
| T1119 |
/workspace/coverage/default/49.flash_ctrl_alert_test.3001164010 |
|
|
Mar 28 02:42:57 PM PDT 24 |
Mar 28 02:43:10 PM PDT 24 |
21774100 ps |
| T1120 |
/workspace/coverage/default/2.flash_ctrl_derr_detect.3742636699 |
|
|
Mar 28 02:31:58 PM PDT 24 |
Mar 28 02:33:44 PM PDT 24 |
176161500 ps |
| T358 |
/workspace/coverage/default/25.flash_ctrl_rw_evict.81410095 |
|
|
Mar 28 02:40:29 PM PDT 24 |
Mar 28 02:40:58 PM PDT 24 |
46303000 ps |
| T1121 |
/workspace/coverage/default/33.flash_ctrl_smoke.3935150607 |
|
|
Mar 28 02:41:27 PM PDT 24 |
Mar 28 02:43:30 PM PDT 24 |
74779900 ps |
| T1122 |
/workspace/coverage/default/22.flash_ctrl_rw_evict_all_en.3434219322 |
|
|
Mar 28 02:39:54 PM PDT 24 |
Mar 28 02:40:25 PM PDT 24 |
70991300 ps |
| T1123 |
/workspace/coverage/default/8.flash_ctrl_ro_derr.1525255591 |
|
|
Mar 28 02:35:29 PM PDT 24 |
Mar 28 02:38:20 PM PDT 24 |
7703823700 ps |
| T1124 |
/workspace/coverage/default/37.flash_ctrl_rw_evict_all_en.470866114 |
|
|
Mar 28 02:42:03 PM PDT 24 |
Mar 28 02:42:32 PM PDT 24 |
48984100 ps |
| T1125 |
/workspace/coverage/default/30.flash_ctrl_rw_evict.2197224365 |
|
|
Mar 28 02:41:05 PM PDT 24 |
Mar 28 02:41:36 PM PDT 24 |
27648300 ps |
| T1126 |
/workspace/coverage/default/15.flash_ctrl_alert_test.1985426381 |
|
|
Mar 28 02:38:27 PM PDT 24 |
Mar 28 02:38:41 PM PDT 24 |
45575800 ps |
| T1127 |
/workspace/coverage/default/12.flash_ctrl_mp_regions.1802518753 |
|
|
Mar 28 02:37:14 PM PDT 24 |
Mar 28 02:50:08 PM PDT 24 |
10650351000 ps |
| T1128 |
/workspace/coverage/default/18.flash_ctrl_mp_regions.3450792042 |
|
|
Mar 28 02:39:20 PM PDT 24 |
Mar 28 02:45:21 PM PDT 24 |
56858762200 ps |
| T1129 |
/workspace/coverage/default/37.flash_ctrl_intr_rd_slow_flash.3297024723 |
|
|
Mar 28 02:42:01 PM PDT 24 |
Mar 28 02:45:40 PM PDT 24 |
32229215300 ps |
| T1130 |
/workspace/coverage/default/19.flash_ctrl_invalid_op.3982661000 |
|
|
Mar 28 02:39:41 PM PDT 24 |
Mar 28 02:40:53 PM PDT 24 |
4557226600 ps |
| T1131 |
/workspace/coverage/default/2.flash_ctrl_intr_rd.3313659710 |
|
|
Mar 28 02:32:16 PM PDT 24 |
Mar 28 02:34:50 PM PDT 24 |
1164358700 ps |
| T1132 |
/workspace/coverage/default/0.flash_ctrl_erase_suspend.738289111 |
|
|
Mar 28 02:30:56 PM PDT 24 |
Mar 28 02:38:59 PM PDT 24 |
29983328400 ps |
| T1133 |
/workspace/coverage/default/43.flash_ctrl_hw_sec_otp.1369380090 |
|
|
Mar 28 02:42:21 PM PDT 24 |
Mar 28 02:44:15 PM PDT 24 |
1150643900 ps |
| T61 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_rw.517463916 |
|
|
Mar 28 12:42:50 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
59085400 ps |
| T62 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3090949097 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:50:36 PM PDT 24 |
743849500 ps |
| T63 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2761126242 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
67547100 ps |
| T198 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3765658825 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:50:18 PM PDT 24 |
854254900 ps |
| T253 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2271100705 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:27 PM PDT 24 |
16665000 ps |
| T273 |
/workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.2651460999 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:16 PM PDT 24 |
47877600 ps |
| T270 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3265130849 |
|
|
Mar 28 12:42:14 PM PDT 24 |
Mar 28 12:42:48 PM PDT 24 |
63420900 ps |
| T218 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3777614019 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:38 PM PDT 24 |
49039500 ps |
| T274 |
/workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.3285789652 |
|
|
Mar 28 12:43:05 PM PDT 24 |
Mar 28 12:43:18 PM PDT 24 |
16703300 ps |
| T1134 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1257377245 |
|
|
Mar 28 12:42:25 PM PDT 24 |
Mar 28 12:42:39 PM PDT 24 |
30257300 ps |
| T1135 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.37948191 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
26877500 ps |
| T199 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2142651251 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:49:01 PM PDT 24 |
921893600 ps |
| T271 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3378084203 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
183125500 ps |
| T217 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1318347574 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:50:23 PM PDT 24 |
405173800 ps |
| T219 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.2589952725 |
|
|
Mar 28 12:42:45 PM PDT 24 |
Mar 28 12:58:00 PM PDT 24 |
747268400 ps |
| T214 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.178664098 |
|
|
Mar 28 12:42:47 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
378485500 ps |
| T312 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2977352447 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
218556100 ps |
| T338 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_intr_test.4019512057 |
|
|
Mar 28 12:42:46 PM PDT 24 |
Mar 28 12:43:00 PM PDT 24 |
19788300 ps |
| T1136 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.4214587340 |
|
|
Mar 28 12:42:24 PM PDT 24 |
Mar 28 12:42:41 PM PDT 24 |
44241000 ps |
| T254 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1236598533 |
|
|
Mar 28 12:42:20 PM PDT 24 |
Mar 28 12:42:35 PM PDT 24 |
32025600 ps |
| T1137 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2508986368 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
66550600 ps |
| T340 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.2609026269 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:53 PM PDT 24 |
16384900 ps |
| T215 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.967435922 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
42191400 ps |
| T339 |
/workspace/coverage/cover_reg_top/47.flash_ctrl_intr_test.2082724533 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
16656900 ps |
| T216 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1907825886 |
|
|
Mar 28 12:42:21 PM PDT 24 |
Mar 28 12:42:40 PM PDT 24 |
189715400 ps |
| T1138 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3199129580 |
|
|
Mar 28 12:42:18 PM PDT 24 |
Mar 28 12:42:34 PM PDT 24 |
14298500 ps |
| T344 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.2673639227 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
88969400 ps |
| T317 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.3393641830 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
370112800 ps |
| T424 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.1114522465 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
126446000 ps |
| T421 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.4182461809 |
|
|
Mar 28 12:42:15 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
1453857200 ps |
| T341 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_intr_test.647267884 |
|
|
Mar 28 12:42:11 PM PDT 24 |
Mar 28 12:42:25 PM PDT 24 |
28420900 ps |
| T255 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.4091199089 |
|
|
Mar 28 12:42:14 PM PDT 24 |
Mar 28 12:42:28 PM PDT 24 |
28170700 ps |
| T245 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.280276706 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:54:51 PM PDT 24 |
1377353400 ps |
| T319 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.3619111315 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:47 PM PDT 24 |
2393179500 ps |
| T423 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2653850348 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
122437200 ps |
| T246 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3486427788 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:12 PM PDT 24 |
95334200 ps |
| T422 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1234784802 |
|
|
Mar 28 12:42:10 PM PDT 24 |
Mar 28 12:42:45 PM PDT 24 |
329536300 ps |
| T1139 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.592824768 |
|
|
Mar 28 12:42:18 PM PDT 24 |
Mar 28 12:42:34 PM PDT 24 |
22457100 ps |
| T342 |
/workspace/coverage/cover_reg_top/24.flash_ctrl_intr_test.1012728308 |
|
|
Mar 28 12:42:58 PM PDT 24 |
Mar 28 12:43:12 PM PDT 24 |
15952400 ps |
| T343 |
/workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.1525316745 |
|
|
Mar 28 12:42:52 PM PDT 24 |
Mar 28 12:43:05 PM PDT 24 |
18765100 ps |
| T247 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3097178151 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:03 PM PDT 24 |
94522900 ps |
| T313 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2561743787 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:43:23 PM PDT 24 |
1860937800 ps |
| T248 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2096286227 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
220163900 ps |
| T249 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.2578052903 |
|
|
Mar 28 12:42:51 PM PDT 24 |
Mar 28 12:58:01 PM PDT 24 |
3301495500 ps |
| T256 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.3862239100 |
|
|
Mar 28 12:42:24 PM PDT 24 |
Mar 28 12:42:39 PM PDT 24 |
16355900 ps |
| T1140 |
/workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.3902125128 |
|
|
Mar 28 12:43:00 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
17404800 ps |
| T1141 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3048173555 |
|
|
Mar 28 12:42:46 PM PDT 24 |
Mar 28 12:43:02 PM PDT 24 |
20043200 ps |
| T250 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_tl_errors.383459718 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
551128600 ps |
| T1142 |
/workspace/coverage/cover_reg_top/37.flash_ctrl_intr_test.2649466404 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:08 PM PDT 24 |
37497800 ps |
| T1143 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4230125033 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
41821900 ps |
| T1144 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1141326063 |
|
|
Mar 28 12:42:09 PM PDT 24 |
Mar 28 12:42:25 PM PDT 24 |
13095500 ps |
| T1145 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2304431541 |
|
|
Mar 28 12:42:10 PM PDT 24 |
Mar 28 12:42:29 PM PDT 24 |
318517400 ps |
| T251 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1858846227 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
74406000 ps |
| T371 |
/workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.1898093465 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:10 PM PDT 24 |
77590300 ps |
| T1146 |
/workspace/coverage/cover_reg_top/31.flash_ctrl_intr_test.1573650195 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:08 PM PDT 24 |
24998100 ps |
| T1147 |
/workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.1894054863 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:09 PM PDT 24 |
43873500 ps |
| T252 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1469104219 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
46531100 ps |
| T1148 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.2541076559 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:08 PM PDT 24 |
28436900 ps |
| T314 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.755553666 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
61937700 ps |
| T1149 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.32198887 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
14060600 ps |
| T1150 |
/workspace/coverage/cover_reg_top/35.flash_ctrl_intr_test.3404775061 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:16 PM PDT 24 |
57799800 ps |
| T1151 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.84309473 |
|
|
Mar 28 12:42:35 PM PDT 24 |
Mar 28 12:42:53 PM PDT 24 |
401909500 ps |
| T372 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1645108944 |
|
|
Mar 28 12:42:20 PM PDT 24 |
Mar 28 12:42:38 PM PDT 24 |
318189600 ps |
| T318 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3659206992 |
|
|
Mar 28 12:42:18 PM PDT 24 |
Mar 28 12:42:36 PM PDT 24 |
200597800 ps |
| T278 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4197396601 |
|
|
Mar 28 12:42:45 PM PDT 24 |
Mar 28 12:43:02 PM PDT 24 |
127257700 ps |
| T1152 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.4197334863 |
|
|
Mar 28 12:42:47 PM PDT 24 |
Mar 28 12:43:03 PM PDT 24 |
46879300 ps |
| T1153 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2809752611 |
|
|
Mar 28 12:42:36 PM PDT 24 |
Mar 28 12:42:52 PM PDT 24 |
33473400 ps |
| T1154 |
/workspace/coverage/cover_reg_top/38.flash_ctrl_intr_test.4190932804 |
|
|
Mar 28 12:42:53 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
42937200 ps |
| T1155 |
/workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.357148668 |
|
|
Mar 28 12:43:02 PM PDT 24 |
Mar 28 12:43:15 PM PDT 24 |
57831000 ps |
| T1156 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2074729852 |
|
|
Mar 28 12:42:16 PM PDT 24 |
Mar 28 12:42:31 PM PDT 24 |
26246900 ps |
| T1157 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_intr_test.2180108707 |
|
|
Mar 28 12:42:18 PM PDT 24 |
Mar 28 12:42:31 PM PDT 24 |
55141000 ps |
| T335 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.3324561351 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:50:25 PM PDT 24 |
1433656400 ps |
| T1158 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_intr_test.908011710 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
47432000 ps |
| T1159 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.2928605435 |
|
|
Mar 28 12:42:45 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
31303100 ps |
| T1160 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.2622182478 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
25937100 ps |
| T1161 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.827228753 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
145472800 ps |
| T315 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.4269066711 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:15 PM PDT 24 |
202592800 ps |
| T316 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.1961149370 |
|
|
Mar 28 12:42:58 PM PDT 24 |
Mar 28 12:43:17 PM PDT 24 |
383967000 ps |
| T1162 |
/workspace/coverage/cover_reg_top/45.flash_ctrl_intr_test.658819669 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:08 PM PDT 24 |
25592500 ps |
| T1163 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3951329165 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:43:15 PM PDT 24 |
87552700 ps |
| T1164 |
/workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.3667334086 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:17 PM PDT 24 |
16333100 ps |
| T286 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.841770694 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
197408200 ps |
| T374 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2822829315 |
|
|
Mar 28 12:42:11 PM PDT 24 |
Mar 28 12:48:36 PM PDT 24 |
452060300 ps |
| T1165 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3663276702 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:11 PM PDT 24 |
16810000 ps |
| T1166 |
/workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.714733948 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:08 PM PDT 24 |
66327400 ps |
| T1167 |
/workspace/coverage/cover_reg_top/34.flash_ctrl_intr_test.2595253389 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:10 PM PDT 24 |
15667900 ps |
| T1168 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.929428884 |
|
|
Mar 28 12:42:36 PM PDT 24 |
Mar 28 12:42:49 PM PDT 24 |
12476900 ps |
| T1169 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4172010750 |
|
|
Mar 28 12:42:46 PM PDT 24 |
Mar 28 12:43:02 PM PDT 24 |
302849500 ps |
| T1170 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2177756972 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
165704100 ps |
| T1171 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.763601901 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
105981000 ps |
| T1172 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1795367750 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
21617200 ps |
| T281 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2743675895 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:20 PM PDT 24 |
408950900 ps |
| T282 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3420139569 |
|
|
Mar 28 12:42:11 PM PDT 24 |
Mar 28 12:48:40 PM PDT 24 |
1085899500 ps |
| T1173 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3369977120 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
57569600 ps |
| T381 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.794026571 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:58:00 PM PDT 24 |
2966838000 ps |
| T275 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.368961257 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
114239300 ps |
| T257 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.2560075752 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:27 PM PDT 24 |
20353300 ps |
| T1174 |
/workspace/coverage/cover_reg_top/22.flash_ctrl_intr_test.3149190202 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
39979700 ps |
| T285 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.824044429 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:57:29 PM PDT 24 |
1227445400 ps |
| T1175 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1666114726 |
|
|
Mar 28 12:42:20 PM PDT 24 |
Mar 28 12:42:36 PM PDT 24 |
62667400 ps |
| T1176 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2470386525 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:27 PM PDT 24 |
42265900 ps |
| T1177 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2781736168 |
|
|
Mar 28 12:43:02 PM PDT 24 |
Mar 28 12:43:17 PM PDT 24 |
46238300 ps |
| T1178 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_rw.710446093 |
|
|
Mar 28 12:42:37 PM PDT 24 |
Mar 28 12:42:54 PM PDT 24 |
65010200 ps |
| T1179 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.957509030 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:26 PM PDT 24 |
13517900 ps |
| T1180 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.3689881759 |
|
|
Mar 28 12:42:35 PM PDT 24 |
Mar 28 12:42:50 PM PDT 24 |
82152600 ps |
| T1181 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2303530174 |
|
|
Mar 28 12:42:16 PM PDT 24 |
Mar 28 12:43:21 PM PDT 24 |
4978240700 ps |
| T1182 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2778032909 |
|
|
Mar 28 12:42:15 PM PDT 24 |
Mar 28 12:42:29 PM PDT 24 |
93940500 ps |
| T1183 |
/workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2031723122 |
|
|
Mar 28 12:42:55 PM PDT 24 |
Mar 28 12:43:09 PM PDT 24 |
120273100 ps |
| T1184 |
/workspace/coverage/cover_reg_top/46.flash_ctrl_intr_test.3879097119 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
25779500 ps |
| T1185 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2830870342 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:27 PM PDT 24 |
32662500 ps |
| T1186 |
/workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.2471731500 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:16 PM PDT 24 |
17013100 ps |
| T1187 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.892546653 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
20249800 ps |
| T375 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.4165224875 |
|
|
Mar 28 12:42:47 PM PDT 24 |
Mar 28 12:55:25 PM PDT 24 |
1396785900 ps |
| T272 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1050053938 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
121853000 ps |
| T1188 |
/workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.525696893 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
104937200 ps |
| T276 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.38961380 |
|
|
Mar 28 12:42:20 PM PDT 24 |
Mar 28 12:42:40 PM PDT 24 |
53869000 ps |
| T1189 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.941277433 |
|
|
Mar 28 12:42:24 PM PDT 24 |
Mar 28 12:42:42 PM PDT 24 |
60783100 ps |
| T1190 |
/workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2461872267 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
60993800 ps |
| T1191 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3847371598 |
|
|
Mar 28 12:42:37 PM PDT 24 |
Mar 28 12:42:53 PM PDT 24 |
75094100 ps |
| T1192 |
/workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.3024295079 |
|
|
Mar 28 12:42:53 PM PDT 24 |
Mar 28 12:43:06 PM PDT 24 |
56122900 ps |
| T1193 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.658314742 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
51796600 ps |
| T1194 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_intr_test.2936161902 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
215495400 ps |
| T1195 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.737099127 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:01 PM PDT 24 |
72203600 ps |
| T1196 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_csr_rw.2122937606 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
96893100 ps |
| T1197 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.677852442 |
|
|
Mar 28 12:42:15 PM PDT 24 |
Mar 28 12:48:45 PM PDT 24 |
368337300 ps |
| T1198 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1581757936 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
70416500 ps |
| T287 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.3576261017 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:12 PM PDT 24 |
122953000 ps |
| T1199 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.3481296234 |
|
|
Mar 28 12:42:16 PM PDT 24 |
Mar 28 12:42:30 PM PDT 24 |
14990300 ps |
| T1200 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_intr_test.2561834398 |
|
|
Mar 28 12:42:50 PM PDT 24 |
Mar 28 12:43:03 PM PDT 24 |
25273900 ps |
| T1201 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2767613233 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:12 PM PDT 24 |
19687000 ps |
| T1202 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1425103266 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:43:02 PM PDT 24 |
451853200 ps |
| T1203 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2258581021 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
14359600 ps |
| T1204 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.829526187 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
36067000 ps |
| T1205 |
/workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3656706426 |
|
|
Mar 28 12:42:54 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
16512500 ps |
| T1206 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.348164169 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
60380300 ps |
| T1207 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.798070645 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:49 PM PDT 24 |
345479700 ps |
| T284 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.172770688 |
|
|
Mar 28 12:41:49 PM PDT 24 |
Mar 28 12:42:05 PM PDT 24 |
28644100 ps |
| T1208 |
/workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.1997187898 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:09 PM PDT 24 |
31619100 ps |
| T1209 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3054348135 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:43:00 PM PDT 24 |
65900000 ps |
| T1210 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.2157625 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:43:01 PM PDT 24 |
14486200 ps |
| T1211 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3312017522 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
1119772700 ps |
| T277 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_tl_errors.4278113336 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
126061400 ps |
| T1212 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.1663294665 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:28 PM PDT 24 |
14852800 ps |
| T1213 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2810946134 |
|
|
Mar 28 12:42:22 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
2596524400 ps |
| T1214 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2315188892 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:20 PM PDT 24 |
48008600 ps |
| T1215 |
/workspace/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1491707919 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:53 PM PDT 24 |
11667800 ps |
| T1216 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2448502978 |
|
|
Mar 28 12:42:45 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
236508200 ps |
| T1217 |
/workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3654157490 |
|
|
Mar 28 12:42:46 PM PDT 24 |
Mar 28 12:42:59 PM PDT 24 |
44060400 ps |
| T280 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_tl_errors.4107702521 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:30 PM PDT 24 |
76913100 ps |
| T1218 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.131122611 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
191322900 ps |
| T1219 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3234423025 |
|
|
Mar 28 12:42:52 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
13914900 ps |
| T283 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3905910618 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:50:24 PM PDT 24 |
254818300 ps |
| T1220 |
/workspace/coverage/cover_reg_top/49.flash_ctrl_intr_test.3033608586 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:16 PM PDT 24 |
17190500 ps |
| T1221 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1249228978 |
|
|
Mar 28 12:42:15 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
1916693800 ps |
| T279 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_tl_errors.36197540 |
|
|
Mar 28 12:42:35 PM PDT 24 |
Mar 28 12:42:55 PM PDT 24 |
114300200 ps |
| T1222 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2578470920 |
|
|
Mar 28 12:42:36 PM PDT 24 |
Mar 28 12:43:12 PM PDT 24 |
641604600 ps |
| T380 |
/workspace/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1100649654 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:57:52 PM PDT 24 |
1136883000 ps |
| T1223 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.2963652228 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
32058000 ps |
| T1224 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.2909931586 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
53885000 ps |
| T1225 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3659774715 |
|
|
Mar 28 12:42:59 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
30203300 ps |
| T1226 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2779994948 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:43:01 PM PDT 24 |
88215100 ps |
| T1227 |
/workspace/coverage/cover_reg_top/1.flash_ctrl_mem_walk.524756647 |
|
|
Mar 28 12:42:17 PM PDT 24 |
Mar 28 12:42:30 PM PDT 24 |
84835200 ps |
| T1228 |
/workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3926332189 |
|
|
Mar 28 12:42:47 PM PDT 24 |
Mar 28 12:43:04 PM PDT 24 |
14864000 ps |
| T1229 |
/workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3675557220 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
253767100 ps |
| T1230 |
/workspace/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1623371320 |
|
|
Mar 28 12:43:09 PM PDT 24 |
Mar 28 12:43:26 PM PDT 24 |
34487400 ps |
| T1231 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3282100269 |
|
|
Mar 28 12:42:17 PM PDT 24 |
Mar 28 12:42:33 PM PDT 24 |
18624700 ps |
| T1232 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1470338996 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:43:15 PM PDT 24 |
166221400 ps |
| T1233 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3047021063 |
|
|
Mar 28 12:42:36 PM PDT 24 |
Mar 28 12:43:40 PM PDT 24 |
1271875900 ps |
| T378 |
/workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.702287702 |
|
|
Mar 28 12:42:44 PM PDT 24 |
Mar 28 12:50:21 PM PDT 24 |
1114816900 ps |
| T1234 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3398485242 |
|
|
Mar 28 12:42:56 PM PDT 24 |
Mar 28 12:43:13 PM PDT 24 |
114696000 ps |
| T1235 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_intr_test.1813902778 |
|
|
Mar 28 12:42:43 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
18033800 ps |
| T1236 |
/workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2923577184 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:43:14 PM PDT 24 |
534657700 ps |
| T1237 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.613929919 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:26 PM PDT 24 |
46225800 ps |
| T1238 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_mem_walk.2828909566 |
|
|
Mar 28 12:42:25 PM PDT 24 |
Mar 28 12:42:39 PM PDT 24 |
22562400 ps |
| T1239 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.864660545 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:54 PM PDT 24 |
12867700 ps |
| T1240 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2188211904 |
|
|
Mar 28 12:42:40 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
19397100 ps |
| T1241 |
/workspace/coverage/cover_reg_top/3.flash_ctrl_mem_walk.284236076 |
|
|
Mar 28 12:42:12 PM PDT 24 |
Mar 28 12:42:26 PM PDT 24 |
78580600 ps |
| T1242 |
/workspace/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1672865321 |
|
|
Mar 28 12:43:03 PM PDT 24 |
Mar 28 12:43:18 PM PDT 24 |
441089000 ps |
| T1243 |
/workspace/coverage/cover_reg_top/7.flash_ctrl_intr_test.3529101602 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
15357500 ps |
| T1244 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.971138568 |
|
|
Mar 28 12:42:20 PM PDT 24 |
Mar 28 12:42:36 PM PDT 24 |
21830000 ps |
| T1245 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.2101432962 |
|
|
Mar 28 12:42:10 PM PDT 24 |
Mar 28 12:42:29 PM PDT 24 |
517930200 ps |
| T1246 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2883094764 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:43 PM PDT 24 |
259479700 ps |
| T1247 |
/workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2207582339 |
|
|
Mar 28 12:42:42 PM PDT 24 |
Mar 28 12:42:56 PM PDT 24 |
36368900 ps |
| T1248 |
/workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1401533311 |
|
|
Mar 28 12:42:13 PM PDT 24 |
Mar 28 12:42:51 PM PDT 24 |
25075100 ps |
| T1249 |
/workspace/coverage/cover_reg_top/8.flash_ctrl_tl_errors.4033650306 |
|
|
Mar 28 12:42:38 PM PDT 24 |
Mar 28 12:42:58 PM PDT 24 |
57238100 ps |
| T1250 |
/workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.236975562 |
|
|
Mar 28 12:42:35 PM PDT 24 |
Mar 28 12:42:52 PM PDT 24 |
91325900 ps |
| T1251 |
/workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1712350550 |
|
|
Mar 28 12:42:50 PM PDT 24 |
Mar 28 12:43:07 PM PDT 24 |
66570800 ps |
| T1252 |
/workspace/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2758053633 |
|
|
Mar 28 12:42:41 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
22425000 ps |
| T1253 |
/workspace/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3882431293 |
|
|
Mar 28 12:42:11 PM PDT 24 |
Mar 28 12:42:57 PM PDT 24 |
23404200 ps |
| T1254 |
/workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.2291771121 |
|
|
Mar 28 12:42:39 PM PDT 24 |
Mar 28 12:42:53 PM PDT 24 |
28378500 ps |