Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23329309	1		T1	17210		T2	56		T3	147
full_word	7881891	1		T1	9261		T2	2		T3	3

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31210890	1		T1	26471		T2	58		T3	150
auto[TlIntgErrCmd]	106	1		T42	5		T196	7		T249	1
auto[TlIntgErrData]	103	1		T42	7		T196	9		T249	4
auto[TlIntgErrBoth]	101	1		T42	8		T196	4		T249	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26665457	1		T1	19505		T2	57		T3	142
auto[1]	4545743	1		T1	6966		T2	1		T3	8

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrBoth]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	22638652	1		T1	16316		T2	56		T3	142
auto[TlIntgErrNone]	partial	auto[1]	690378	1		T1	894		T3	5		T4	675
auto[TlIntgErrNone]	full_word	auto[0]	4026653	1		T1	3189		T2	1		T4	4885
auto[TlIntgErrNone]	full_word	auto[1]	3855207	1		T1	6072		T2	1		T3	3
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T42	1		T196	3		T299	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T42	2		T196	4		T249	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T261	1		T357	1		T358	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T42	2		T267	1		T301	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T42	3		T196	4		T249	1
auto[TlIntgErrData]	partial	auto[1]	37	1		T42	3		T196	2		T249	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T196	2		T267	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T42	1		T196	1		T249	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1		T196	1		T249	2		T299	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T42	8		T196	3		T249	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T249	1		T299	1		T265	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	22268	1		T40	66		T41	80		T42	17
full_word	4474660	1		T4	16956		T7	16695		T9	16337

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4496641	1		T4	16956		T7	16695		T9	16337
auto[TlIntgErrCmd]	105	1		T42	9		T196	9		T299	4
auto[TlIntgErrData]	90	1		T42	7		T196	5		T249	5
auto[TlIntgErrBoth]	92	1		T42	3		T196	4		T249	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4468753	1		T4	16956		T7	16695		T9	16337
auto[1]	28175	1		T40	78		T41	90		T42	14

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1272	1		T40	6		T41	12		T193	30
auto[TlIntgErrNone]	partial	auto[1]	20733	1		T40	60		T41	68		T193	744
auto[TlIntgErrNone]	full_word	auto[0]	4467361	1		T4	16956		T7	16695		T9	16337
auto[TlIntgErrNone]	full_word	auto[1]	7275	1		T40	18		T41	22		T193	163
auto[TlIntgErrCmd]	partial	auto[0]	33	1		T42	1		T196	3		T299	1
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T42	7		T196	5		T299	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T354	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T42	1		T196	1		T299	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T42	3		T196	3		T249	3
auto[TlIntgErrData]	partial	auto[1]	34	1		T42	3		T196	2		T249	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T358	1		T359	2		T360	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T42	1		T261	1		T361	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T42	1		T249	1		T299	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T42	2		T196	3		T249	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T263	1		T362	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T196	1		T267	1		T265	1