Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1642104452	1638801512	0	0
CheckNGreaterZero_A	4236	4236	0	0
GntImpliesReady_A	1642104452	460604055	0	0
GntImpliesValid_A	1642104452	460604055	0	0
GrantKnown_A	1642104452	1638801512	0	0
IdxKnown_A	1642104452	1638801512	0	0
IndexIsCorrect_A	1642104452	460604055	0	0
NoReadyValidNoGrant_A	1642104452	182271380	0	0
Priority_A	1642104452	485319479	0	0
ReadyAndValidImplyGrant_A	1642104452	460604055	0	0
ReqAndReadyImplyGrant_A	1642104452	460604055	0	0
ReqImpliesValid_A	1642104452	485319479	0	0
ValidKnown_A	1642104452	1638801512	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	1638801512	0	0
T1	809920	774100	0	0
T2	4548	4192	0	0
T3	12152	9284	0	0
T4	212560	212304	0	0
T5	3281680	3281460	0	0
T6	295696	283364	0	0
T7	479160	478616	0	0
T8	37184	36808	0	0
T20	302732	302524	0	0
T21	523412	491784	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4236	4236	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T8	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	460604055	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	41644	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	66096	0	0
T8	37184	7322	0	0
T9	1793638	30994	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	460604055	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	41644	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	66096	0	0
T8	37184	7322	0	0
T9	1793638	30994	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	1638801512	0	0
T1	809920	774100	0	0
T2	4548	4192	0	0
T3	12152	9284	0	0
T4	212560	212304	0	0
T5	3281680	3281460	0	0
T6	295696	283364	0	0
T7	479160	478616	0	0
T8	37184	36808	0	0
T20	302732	302524	0	0
T21	523412	491784	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	1638801512	0	0
T1	809920	774100	0	0
T2	4548	4192	0	0
T3	12152	9284	0	0
T4	212560	212304	0	0
T5	3281680	3281460	0	0
T6	295696	283364	0	0
T7	479160	478616	0	0
T8	37184	36808	0	0
T20	302732	302524	0	0
T21	523412	491784	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	460604055	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	41644	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	66096	0	0
T8	37184	7322	0	0
T9	1793638	30994	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	182271380	0	0
T1	404960	44512	0	0
T2	2274	256	0	0
T3	6076	804	0	0
T4	212560	123868	0	0
T5	3281680	5406	0	0
T6	295696	14920	0	0
T7	479160	182732	0	0
T8	37184	666	0	0
T9	1793638	971884	0	0
T14	757520	1048576	0	0
T16	0	1048816	0	0
T20	302732	1362	0	0
T21	523412	40328	0	0
T24	10038	1180	0	0
T58	0	730	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	485319479	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	44512	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	69802	0	0
T8	37184	7322	0	0
T9	1793638	316838	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	460604055	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	41644	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	66096	0	0
T8	37184	7322	0	0
T9	1793638	30994	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	460604055	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	41644	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	66096	0	0
T8	37184	7322	0	0
T9	1793638	30994	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	485319479	0	0
T1	404960	176256	0	0
T2	2274	64	0	0
T3	6076	204	0	0
T4	212560	44512	0	0
T5	3281680	1503872	0	0
T6	295696	51740	0	0
T7	479160	69802	0	0
T8	37184	7322	0	0
T9	1793638	316838	0	0
T14	757520	255794	0	0
T20	302732	145450	0	0
T21	523412	159504	0	0
T22	0	16810	0	0
T24	10038	478	0	0
T51	0	58450	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642104452	1638801512	0	0
T1	809920	774100	0	0
T2	4548	4192	0	0
T3	12152	9284	0	0
T4	212560	212304	0	0
T5	3281680	3281460	0	0
T6	295696	283364	0	0
T7	479160	478616	0	0
T8	37184	36808	0	0
T20	302732	302524	0	0
T21	523412	491784	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410526113	409700378	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	410526113	125421855	0	0
GntImpliesValid_A	410526113	125421855	0	0
GrantKnown_A	410526113	409700378	0	0
IdxKnown_A	410526113	409700378	0	0
IndexIsCorrect_A	410526113	125421855	0	0
NoReadyValidNoGrant_A	410526113	47155485	0	0
Priority_A	410526113	131673159	0	0
ReadyAndValidImplyGrant_A	410526113	125421855	0	0
ReqAndReadyImplyGrant_A	410526113	125421855	0	0
ReqImpliesValid_A	410526113	131673159	0	0
ValidKnown_A	410526113	409700378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125421855	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125421855	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125421855	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	47155485	0	0
T1	202480	22256	0	0
T2	1137	128	0	0
T3	3038	402	0	0
T4	53140	31524	0	0
T5	820420	1135	0	0
T6	73924	7460	0	0
T7	119790	55064	0	0
T8	9296	214	0	0
T20	75683	388	0	0
T21	130853	20164	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	131673159	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	11077	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20951	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125421855	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125421855	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	131673159	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	11077	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20951	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410526113	409700378	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	410526113	125225850	0	0
GntImpliesValid_A	410526113	125225850	0	0
GrantKnown_A	410526113	409700378	0	0
IdxKnown_A	410526113	409700378	0	0
IndexIsCorrect_A	410526113	125225850	0	0
NoReadyValidNoGrant_A	410526113	47155533	0	0
Priority_A	410526113	131477106	0	0
ReadyAndValidImplyGrant_A	410526113	125225850	0	0
ReqAndReadyImplyGrant_A	410526113	125225850	0	0
ReqImpliesValid_A	410526113	131477106	0	0
ValidKnown_A	410526113	409700378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125225850	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125225850	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125225850	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	47155533	0	0
T1	202480	22256	0	0
T2	1137	128	0	0
T3	3038	402	0	0
T4	53140	31524	0	0
T5	820420	1135	0	0
T6	73924	7460	0	0
T7	119790	55064	0	0
T8	9296	214	0	0
T20	75683	388	0	0
T21	130853	20164	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	131477106	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	11077	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20951	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125225850	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	125225850	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	10541	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20264	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	131477106	0	0
T1	202480	88128	0	0
T2	1137	32	0	0
T3	3038	102	0	0
T4	53140	11077	0	0
T5	820420	34691	0	0
T6	73924	25870	0	0
T7	119790	20951	0	0
T8	9296	1669	0	0
T20	75683	67885	0	0
T21	130853	79752	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T5,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T5,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410526113	409700378	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	410526113	104978175	0	0
GntImpliesValid_A	410526113	104978175	0	0
GrantKnown_A	410526113	409700378	0	0
IdxKnown_A	410526113	409700378	0	0
IndexIsCorrect_A	410526113	104978175	0	0
NoReadyValidNoGrant_A	410526113	43980181	0	0
Priority_A	410526113	111084607	0	0
ReadyAndValidImplyGrant_A	410526113	104978175	0	0
ReqAndReadyImplyGrant_A	410526113	104978175	0	0
ReqImpliesValid_A	410526113	111084607	0	0
ValidKnown_A	410526113	409700378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	43980181	0	0
T4	53140	30410	0	0
T5	820420	1568	0	0
T6	73924	0	0	0
T7	119790	36302	0	0
T8	9296	119	0	0
T9	896819	485942	0	0
T14	378760	524288	0	0
T16	0	524408	0	0
T20	75683	293	0	0
T21	130853	0	0	0
T24	5019	590	0	0
T58	0	365	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	111084607	0	0
T4	53140	11179	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	13950	0	0
T8	9296	1992	0	0
T9	896819	158419	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	111084607	0	0
T4	53140	11179	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	13950	0	0
T8	9296	1992	0	0
T9	896819	158419	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T5,T20
1	0	Covered	T4,T7,T9

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T7,T9
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T9
1	0	Covered	T4,T5,T20
1	1	Covered	T4,T7,T9

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T5,T20

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T7,T9
1	1	Covered	T4,T5,T20

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T7,T9

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	410526113	409700378	0	0
CheckNGreaterZero_A	1059	1059	0	0
GntImpliesReady_A	410526113	104978175	0	0
GntImpliesValid_A	410526113	104978175	0	0
GrantKnown_A	410526113	409700378	0	0
IdxKnown_A	410526113	409700378	0	0
IndexIsCorrect_A	410526113	104978175	0	0
NoReadyValidNoGrant_A	410526113	43980181	0	0
Priority_A	410526113	111084607	0	0
ReadyAndValidImplyGrant_A	410526113	104978175	0	0
ReqAndReadyImplyGrant_A	410526113	104978175	0	0
ReqImpliesValid_A	410526113	111084607	0	0
ValidKnown_A	410526113	409700378	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1059	1059	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	43980181	0	0
T4	53140	30410	0	0
T5	820420	1568	0	0
T6	73924	0	0	0
T7	119790	36302	0	0
T8	9296	119	0	0
T9	896819	485942	0	0
T14	378760	524288	0	0
T16	0	524408	0	0
T20	75683	293	0	0
T21	130853	0	0	0
T24	5019	590	0	0
T58	0	365	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	111084607	0	0
T4	53140	11179	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	13950	0	0
T8	9296	1992	0	0
T9	896819	158419	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	104978175	0	0
T4	53140	10281	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	12784	0	0
T8	9296	1992	0	0
T9	896819	15497	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	111084607	0	0
T4	53140	11179	0	0
T5	820420	717245	0	0
T6	73924	0	0	0
T7	119790	13950	0	0
T8	9296	1992	0	0
T9	896819	158419	0	0
T14	378760	127897	0	0
T20	75683	4840	0	0
T21	130853	0	0	0
T22	0	8405	0	0
T24	5019	239	0	0
T51	0	29225	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	410526113	409700378	0	0
T1	202480	193525	0	0
T2	1137	1048	0	0
T3	3038	2321	0	0
T4	53140	53076	0	0
T5	820420	820365	0	0
T6	73924	70841	0	0
T7	119790	119654	0	0
T8	9296	9202	0	0
T20	75683	75631	0	0
T21	130853	122946	0	0