Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27429545	1		T1	142		T2	523		T3	2778
full_word	7866684	1		T1	57		T2	154		T3	604

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35295929	1		T1	199		T2	677		T3	3382
auto[TlIntgErrCmd]	102	1		T60	8		T238	4		T239	4
auto[TlIntgErrData]	101	1		T60	7		T238	3		T239	6
auto[TlIntgErrBoth]	97	1		T60	5		T238	3		T239	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30820437	1		T1	147		T2	577		T3	2939
auto[1]	4475792	1		T1	52		T2	100		T3	443

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26773834	1		T1	133		T2	507		T3	2723
auto[TlIntgErrNone]	partial	auto[1]	655435	1		T1	9		T2	16		T3	55
auto[TlIntgErrNone]	full_word	auto[0]	4046471	1		T1	14		T2	70		T3	216
auto[TlIntgErrNone]	full_word	auto[1]	3820189	1		T1	43		T2	84		T3	388
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T60	1		T238	2		T239	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T60	5		T238	2		T239	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T60	2		T347	2		T348	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T239	1		T346	1		T344	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T60	4		T238	2		T346	1
auto[TlIntgErrData]	partial	auto[1]	51	1		T60	3		T238	1		T239	5
auto[TlIntgErrData]	full_word	auto[0]	5	1		T239	1		T347	1		T349	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T344	1		T350	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T60	2		T239	2		T346	1
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T60	3		T238	1		T239	8
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T238	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T238	1		T352	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20838	1		T60	17		T170	587		T173	618
full_word	4472512	1		T2	7		T3	18		T14	9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4493073	1		T2	7		T3	18		T14	9
auto[TlIntgErrCmd]	78	1		T60	7		T238	1		T239	6
auto[TlIntgErrData]	97	1		T60	4		T238	5		T239	6
auto[TlIntgErrBoth]	102	1		T60	6		T238	3		T239	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4466865	1		T2	7		T3	18		T14	9
auto[1]	26485	1		T60	14		T170	684		T173	755

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1286	1		T170	30		T173	19		T171	1
auto[TlIntgErrNone]	partial	auto[1]	19298	1		T170	557		T173	599		T171	16
auto[TlIntgErrNone]	full_word	auto[0]	4465463	1		T2	7		T3	18		T14	9
auto[TlIntgErrNone]	full_word	auto[1]	7026	1		T170	127		T173	156		T171	5
auto[TlIntgErrCmd]	partial	auto[0]	25	1		T238	1		T239	2		T346	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T60	7		T239	4		T346	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T351	1		T353	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T354	1		T349	1		T355	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T60	1		T238	4		T239	1
auto[TlIntgErrData]	partial	auto[1]	39	1		T60	3		T238	1		T239	5
auto[TlIntgErrData]	full_word	auto[0]	8	1		T350	1		T352	1		T342	3
auto[TlIntgErrData]	full_word	auto[1]	7	1		T346	1		T274	1		T341	2
auto[TlIntgErrBoth]	partial	auto[0]	37	1		T60	2		T238	1		T239	3
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T60	4		T238	2		T239	5
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T344	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T350	1		T347	1		-	-