Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.38 96.63 83.96 100.00 91.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.03 97.54 92.87 96.90 100.00 96.95 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 97.56 100.00 93.85 95.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 91.95 75.93 91.89 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.82 99.16 93.71 100.00 100.00 96.23
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.40 98.88 95.28 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.02 97.79 94.29 100.00 100.00 98.09 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 95.38 100.00 100.00 96.49 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 92.22 100.00 88.89 100.00 80.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.89 99.16 94.05 100.00 100.00 96.23
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions10610195.28
Logical10610195.28
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11CoveredT89,T70,T211

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT89,T70,T211

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT2,T3,T14
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T14,T4
110Not Covered
111CoveredT2,T3,T14

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT3,T14,T4
101CoveredT2,T3,T14
110CoveredT64,T69
111CoveredT2,T3,T14

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T14,T4
11CoveredT2,T3,T14

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11CoveredT2,T3,T14

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT63,T65,T93
10CoveredT1,T2,T3
11CoveredT2,T3,T14

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T16,T24
11CoveredT1,T2,T3

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT64,T69
10CoveredT212,T210,T213

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT212,T210,T213

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT1,T2,T3
11CoveredT64,T69

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT14,T16,T24
10CoveredT1,T2,T3
11CoveredT14,T24,T26

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T22,T23
10CoveredT14,T16,T24

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT192

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT2,T3,T14
10CoveredT192
11CoveredT192

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T14

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T14
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT192

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T17

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T17

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 340 Covered T14,T16,T24
StCtrlProg 338 Covered T1,T2,T3
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T1,T10,T11
StIdle 348 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 368 Covered T14,T16,T24
StCtrlProg->StIdle 358 Covered T1,T2,T3
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T14,T16,T24
StIdle->StCtrlProg 338 Covered T1,T2,T3
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T1,T10,T11



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 2 100.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T192
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T5,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T89,T70,T211
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T192
0 0 0 Covered T2,T3,T14


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T2,T3
StIdle 0 0 0 1 - - - Covered T14,T16,T24
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T2,T3
StCtrlProg - - - - - 0 - Covered T1,T2,T3
StCtrl - - - - - - 1 Covered T14,T24,T26
StCtrl - - - - - - 0 Covered T14,T16,T24
StDisable - - - - - - - Covered T1,T10,T11
default - - - - - - - Covered T11,T12,T13


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 825539946 4391376 0 0
CtrlPrio_A 825539946 4391346 0 0
HostTransIdleChk_A 825539946 46617407 0 0
NoRemainder_A 2126 2126 0 0
OneHotReqs_A 825539946 823886952 0 0
Pow2Multiple_A 2126 2126 0 0
RdTxnCheck_A 825138806 823485812 0 0
u_state_regs_A 825539946 823886952 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825539946 4391376 0 0
T4 216010 6705 0 0
T5 267428 5410 0 0
T6 103702 0 0 0
T21 540548 0 0 0
T24 768372 0 0 0
T26 325532 0 0 0
T30 0 3521 0 0
T32 0 4685 0 0
T33 0 11122 0 0
T34 0 15256 0 0
T51 0 4016 0 0
T57 0 15944 0 0
T73 0 75396 0 0
T77 6436 0 0 0
T78 8924 0 0 0
T113 7026 0 0 0
T114 3168 0 0 0
T189 0 3000 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825539946 4391346 0 0
T4 216010 6705 0 0
T5 267428 5410 0 0
T6 103702 0 0 0
T21 540548 0 0 0
T24 768372 0 0 0
T26 325532 0 0 0
T30 0 3521 0 0
T32 0 4685 0 0
T33 0 11122 0 0
T34 0 15256 0 0
T51 0 4016 0 0
T57 0 15944 0 0
T73 0 75396 0 0
T77 6436 0 0 0
T78 8924 0 0 0
T113 7026 0 0 0
T114 3168 0 0 0
T189 0 3000 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825539946 46617407 0 0
T2 3261 28 0 0
T3 8371 35 0 0
T4 108005 57970 0 0
T5 0 57560 0 0
T6 0 222 0 0
T10 1286 0 0 0
T11 255244 57 0 0
T14 11458 27 0 0
T15 4360 0 0 0
T16 7842 0 0 0
T17 3496 0 0 0
T18 1135254 0 0 0
T19 0 514 0 0
T20 0 429 0 0
T24 384186 0 0 0
T30 0 37193 0 0
T33 0 129912 0 0
T55 5024 0 0 0
T57 0 142697 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2126 2126 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825539946 823886952 0 0
T1 2208 2030 0 0
T2 6522 6192 0 0
T3 16742 16374 0 0
T10 1286 1172 0 0
T11 255244 204756 0 0
T14 11458 11146 0 0
T15 4360 4234 0 0
T16 7842 6280 0 0
T17 3496 3386 0 0
T18 1135254 1135236 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2126 2126 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T10 2 2 0 0
T11 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825138806 823485812 0 0
T1 2208 2030 0 0
T2 6522 6192 0 0
T3 16742 16374 0 0
T10 1286 1172 0 0
T11 174056 123568 0 0
T14 11458 11146 0 0
T15 4360 4234 0 0
T16 7842 6280 0 0
T17 3496 3386 0 0
T18 1135254 1135236 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 825539946 823886952 0 0
T1 2208 2030 0 0
T2 6522 6192 0 0
T3 16742 16374 0 0
T10 1286 1172 0 0
T11 255244 204756 0 0
T14 11458 11146 0 0
T15 4360 4234 0 0
T16 7842 6280 0 0
T17 3496 3386 0 0
T18 1135254 1135236 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL898696.63
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS2024375.00
ALWAYS2146583.33
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 0 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 0 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1068983.96
Logical1068983.96
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T4,T5
11Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T14,T15
10CoveredT14,T11,T4
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT14,T11,T4
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT14,T11,T4
10CoveredT1,T14,T15
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT14,T11,T4
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT14,T4,T5
110Not Covered
111CoveredT14,T4,T5

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT14,T4,T5
101CoveredT14,T11,T4
110Not Covered
111CoveredT14,T4,T5

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT14,T4,T5
11CoveredT14,T4,T5

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT14,T15,T4
10CoveredT14,T11,T4
11CoveredT14,T4,T5

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T4,T5

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T14,T15
11CoveredT14,T4,T5

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT14,T4,T5
10CoveredT1,T14,T15
11CoveredT4,T5,T30

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T15,T17
11CoveredT14,T15,T4

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT2,T3,T15
10CoveredT24,T26,T21
11CoveredT1,T15,T17

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T14,T15
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT14,T4,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T4,T5

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T4,T5

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T4,T5

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T4,T5

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T15,T17
11CoveredT14,T15,T4

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T15,T4
11CoveredT1,T15,T17

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT14,T16,T24
10CoveredT1,T14,T15
11CoveredT24,T26,T21

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T22,T23
10CoveredT14,T16,T24

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT14,T11,T4
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T11,T4

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T15,T17
11CoveredT14,T15,T4

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T4,T5
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T4,T5
10CoveredT1,T17,T6

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T4,T5
10CoveredT1,T17,T6

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T17,T6

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T17,T6

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 340 Covered T24,T26,T21
StCtrlProg 338 Covered T1,T15,T17
StCtrlRead 336 Covered T14,T15,T4
StDisable 334 Covered T1,T10,T11
StIdle 348 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 368 Covered T24,T26,T21
StCtrlProg->StIdle 358 Covered T1,T15,T17
StCtrlRead->StIdle 348 Covered T14,T15,T4
StIdle->StCtrl 340 Covered T24,T26,T21
StIdle->StCtrlProg 338 Covered T1,T15,T17
StIdle->StCtrlRead 336 Covered T14,T15,T4
StIdle->StDisable 334 Covered T1,T10,T11



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 42 91.30
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 2 66.67
IF 214 4 3 75.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T14,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T14,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T14,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T14,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T14,T4,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T17,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T17,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T14,T15
0 0 1 Covered T4,T5,T30
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T14,T11,T4


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T14,T15


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T10,T11
StIdle 0 1 - - - - - Covered T14,T15,T4
StIdle 0 0 1 - - - - Covered T1,T15,T17
StIdle 0 0 0 1 - - - Covered T24,T26,T21
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T14,T15,T4
StCtrlRead - - - - 0 - - Covered T14,T15,T4
StCtrlProg - - - - - 1 - Covered T1,T15,T17
StCtrlProg - - - - - 0 - Covered T1,T15,T17
StCtrl - - - - - - 1 Covered T24,T26,T21
StCtrl - - - - - - 0 Covered T24,T26,T21
StDisable - - - - - - - Covered T1,T10,T11
default - - - - - - - Covered T11,T12,T13


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 412769973 2146997 0 0
CtrlPrio_A 412769973 2146997 0 0
HostTransIdleChk_A 412769973 22864796 0 0
NoRemainder_A 1063 1063 0 0
OneHotReqs_A 412769973 411943476 0 0
Pow2Multiple_A 1063 1063 0 0
RdTxnCheck_A 412569403 411742906 0 0
u_state_regs_A 412769973 411943476 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 2146997 0 0
T4 108005 3690 0 0
T5 133714 2348 0 0
T6 51851 0 0 0
T21 270274 0 0 0
T24 384186 0 0 0
T26 162766 0 0 0
T30 0 2015 0 0
T32 0 2726 0 0
T33 0 6291 0 0
T34 0 8642 0 0
T51 0 2245 0 0
T57 0 7404 0 0
T73 0 28016 0 0
T77 3218 0 0 0
T78 4462 0 0 0
T113 3513 0 0 0
T114 1584 0 0 0
T189 0 1220 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 2146997 0 0
T4 108005 3690 0 0
T5 133714 2348 0 0
T6 51851 0 0 0
T21 270274 0 0 0
T24 384186 0 0 0
T26 162766 0 0 0
T30 0 2015 0 0
T32 0 2726 0 0
T33 0 6291 0 0
T34 0 8642 0 0
T51 0 2245 0 0
T57 0 7404 0 0
T73 0 28016 0 0
T77 3218 0 0 0
T78 4462 0 0 0
T113 3513 0 0 0
T114 1584 0 0 0
T189 0 1220 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 22864796 0 0
T4 108005 30339 0 0
T5 0 28922 0 0
T6 0 171 0 0
T10 643 0 0 0
T11 127622 27 0 0
T14 5729 27 0 0
T15 2180 0 0 0
T16 3921 0 0 0
T17 1748 0 0 0
T18 567627 0 0 0
T19 0 179 0 0
T20 0 429 0 0
T24 384186 0 0 0
T30 0 20973 0 0
T33 0 69772 0 0
T55 2512 0 0 0
T57 0 59120 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 411943476 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412569403 411742906 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 87028 61784 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 411943476 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL898898.88
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS2286583.33
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 0 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions10610195.28
Logical10610195.28
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T4
11CoveredT89,T70,T211

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T11
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT89,T70,T211

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT2,T3,T11
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT2,T3,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT2,T3,T11
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T5,T6
110Not Covered
111CoveredT2,T3,T4

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT3,T5,T6
101CoveredT2,T3,T11
110CoveredT64,T69
111CoveredT2,T3,T4

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT2,T4,T5
11CoveredT2,T3,T4

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T11
11CoveredT2,T3,T4

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT63,T65,T93
10CoveredT1,T2,T3
11CoveredT2,T3,T4

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT4,T5,T6

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT14,T15,T4
10CoveredT2,T3,T14
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T15,T17
10CoveredT14,T16,T24
11CoveredT2,T3,T15

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT64,T69
10CoveredT212,T210,T213

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT212,T210,T213

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT2,T3,T4
10CoveredT1,T2,T3
11CoveredT64,T69

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T4

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T3,T15

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT14,T16,T24
10CoveredT1,T2,T3
11CoveredT14,T24,T26

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T22,T23
10CoveredT14,T16,T24

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT192

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT2,T3,T11
10CoveredT192
11CoveredT192

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T11

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T14
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT2,T3,T4
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT192

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT11,T12,T13
10CoveredT11,T12,T13

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T6,T56

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT2,T6,T56

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T56

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T6,T56

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
states   Line No.   Covered   Tests   
StCtrl 340 Covered T14,T16,T24
StCtrlProg 338 Covered T2,T3,T15
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T1,T10,T11
StIdle 348 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StCtrl->StIdle 368 Covered T14,T16,T24
StCtrlProg->StIdle 358 Covered T2,T3,T15
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T14,T16,T24
StIdle->StCtrlProg 338 Covered T2,T3,T15
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T1,T10,T11



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 2 100.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 3 75.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T4
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T56
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T2,T6,T56
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Covered T192
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T4,T5,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T89,T70,T211
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T192
0 0 0 Covered T2,T3,T11


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T1,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T2,T3,T15
StIdle 0 0 0 1 - - - Covered T14,T16,T24
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T2,T3,T15
StCtrlProg - - - - - 0 - Covered T2,T3,T15
StCtrl - - - - - - 1 Covered T14,T24,T26
StCtrl - - - - - - 0 Covered T14,T16,T24
StDisable - - - - - - - Covered T1,T10,T11
default - - - - - - - Covered T11,T12,T13


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
ArbCntMax_A 412769973 2244379 0 0
CtrlPrio_A 412769973 2244349 0 0
HostTransIdleChk_A 412769973 23752611 0 0
NoRemainder_A 1063 1063 0 0
OneHotReqs_A 412769973 411943476 0 0
Pow2Multiple_A 1063 1063 0 0
RdTxnCheck_A 412569403 411742906 0 0
u_state_regs_A 412769973 411943476 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 2244379 0 0
T4 108005 3015 0 0
T5 133714 3062 0 0
T6 51851 0 0 0
T21 270274 0 0 0
T24 384186 0 0 0
T26 162766 0 0 0
T30 0 1506 0 0
T32 0 1959 0 0
T33 0 4831 0 0
T34 0 6614 0 0
T51 0 1771 0 0
T57 0 8540 0 0
T73 0 47380 0 0
T77 3218 0 0 0
T78 4462 0 0 0
T113 3513 0 0 0
T114 1584 0 0 0
T189 0 1780 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 2244349 0 0
T4 108005 3015 0 0
T5 133714 3062 0 0
T6 51851 0 0 0
T21 270274 0 0 0
T24 384186 0 0 0
T26 162766 0 0 0
T30 0 1506 0 0
T32 0 1959 0 0
T33 0 4831 0 0
T34 0 6614 0 0
T51 0 1771 0 0
T57 0 8540 0 0
T73 0 47380 0 0
T77 3218 0 0 0
T78 4462 0 0 0
T113 3513 0 0 0
T114 1584 0 0 0
T189 0 1780 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 23752611 0 0
T2 3261 28 0 0
T3 8371 35 0 0
T4 0 27631 0 0
T5 0 28638 0 0
T6 0 51 0 0
T10 643 0 0 0
T11 127622 30 0 0
T14 5729 0 0 0
T15 2180 0 0 0
T16 3921 0 0 0
T17 1748 0 0 0
T18 567627 0 0 0
T19 0 335 0 0
T30 0 16220 0 0
T33 0 60140 0 0
T55 2512 0 0 0
T57 0 83577 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 411943476 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1063 1063 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412569403 411742906 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 87028 61784 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412769973 411943476 0 0
T1 1104 1015 0 0
T2 3261 3096 0 0
T3 8371 8187 0 0
T10 643 586 0 0
T11 127622 102378 0 0
T14 5729 5573 0 0
T15 2180 2117 0 0
T16 3921 3140 0 0
T17 1748 1693 0 0
T18 567627 567618 0 0