Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T14
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T14,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T14

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T14
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T14,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T14

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1651079892	1647773904	0	0
CheckNGreaterZero_A	4252	4252	0	0
GntImpliesReady_A	1651079892	465876769	0	0
GntImpliesValid_A	1651079892	465876769	0	0
GrantKnown_A	1651079892	1647773904	0	0
IdxKnown_A	1651079892	1647773904	0	0
IndexIsCorrect_A	1651079892	465876769	0	0
NoReadyValidNoGrant_A	1651079892	182640737	0	0
Priority_A	1651079892	490383910	0	0
ReadyAndValidImplyGrant_A	1651079892	465876769	0	0
ReqAndReadyImplyGrant_A	1651079892	465876769	0	0
ReqImpliesValid_A	1651079892	490383910	0	0
ValidKnown_A	1651079892	1647773904	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	1647773904	0	0
T1	4416	4060	0	0
T2	13044	12384	0	0
T3	33484	32748	0	0
T10	2572	2344	0	0
T11	510488	409512	0	0
T14	22916	22292	0	0
T15	8720	8468	0	0
T16	15684	12560	0	0
T17	6992	6772	0	0
T18	2270508	2270472	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4252	4252	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	465876769	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	30398	0	0
T5	0	28934	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	465876769	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	30398	0	0
T5	0	28934	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	1647773904	0	0
T1	4416	4060	0	0
T2	13044	12384	0	0
T3	33484	32748	0	0
T10	2572	2344	0	0
T11	510488	409512	0	0
T14	22916	22292	0	0
T15	8720	8468	0	0
T16	15684	12560	0	0
T17	6992	6772	0	0
T18	2270508	2270472	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	1647773904	0	0
T1	4416	4060	0	0
T2	13044	12384	0	0
T3	33484	32748	0	0
T10	2572	2344	0	0
T11	510488	409512	0	0
T14	22916	22292	0	0
T15	8720	8468	0	0
T16	15684	12560	0	0
T17	6992	6772	0	0
T18	2270508	2270472	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	465876769	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	30398	0	0
T5	0	28934	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	182640737	0	0
T1	2208	256	0	0
T2	6522	850	0	0
T3	16742	900	0	0
T4	216010	83978	0	0
T5	0	82030	0	0
T6	0	5334	0	0
T10	2572	272	0	0
T11	510488	8806	0	0
T14	22916	1480	0	0
T15	8720	318	0	0
T16	15684	1340	0	0
T17	6992	256	0	0
T18	2270508	3392	0	0
T21	0	300	0	0
T24	768372	9326	0	0
T26	0	3300	0	0
T30	0	51004	0	0
T55	5024	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	490383910	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	32622	0	0
T5	0	30764	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	465876769	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	30398	0	0
T5	0	28934	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	465876769	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	30398	0	0
T5	0	28934	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	490383910	0	0
T1	4416	302	0	0
T2	13044	1132	0	0
T3	33484	9556	0	0
T4	0	32622	0	0
T5	0	30764	0	0
T10	2572	68	0	0
T11	510488	0	0	0
T14	22916	6256	0	0
T15	8720	1868	0	0
T16	15684	396	0	0
T17	6992	952	0	0
T18	2270508	1129910	0	0
T21	0	397360	0	0
T24	0	113924	0	0
T26	0	50728	0	0
T55	0	64	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1651079892	1647773904	0	0
T1	4416	4060	0	0
T2	13044	12384	0	0
T3	33484	32748	0	0
T10	2572	2344	0	0
T11	510488	409512	0	0
T14	22916	22292	0	0
T15	8720	8468	0	0
T16	15684	12560	0	0
T17	6992	6772	0	0
T18	2270508	2270472	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412769973	411943476	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	412769973	131736878	0	0
GntImpliesValid_A	412769973	131736878	0	0
GrantKnown_A	412769973	411943476	0	0
IdxKnown_A	412769973	411943476	0	0
IndexIsCorrect_A	412769973	131736878	0	0
NoReadyValidNoGrant_A	412769973	48253195	0	0
Priority_A	412769973	137933758	0	0
ReadyAndValidImplyGrant_A	412769973	131736878	0	0
ReqAndReadyImplyGrant_A	412769973	131736878	0	0
ReqImpliesValid_A	412769973	137933758	0	0
ValidKnown_A	412769973	411943476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131736878	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131736878	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131736878	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	48253195	0	0
T1	1104	128	0	0
T2	3261	425	0	0
T3	8371	450	0	0
T10	643	136	0	0
T11	127622	2982	0	0
T14	5729	256	0	0
T15	2180	128	0	0
T16	3921	670	0	0
T17	1748	128	0	0
T18	567627	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	137933758	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131736878	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131736878	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	137933758	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412769973	411943476	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	412769973	131528417	0	0
GntImpliesValid_A	412769973	131528417	0	0
GrantKnown_A	412769973	411943476	0	0
IdxKnown_A	412769973	411943476	0	0
IndexIsCorrect_A	412769973	131528417	0	0
NoReadyValidNoGrant_A	412769973	48253196	0	0
Priority_A	412769973	137725296	0	0
ReadyAndValidImplyGrant_A	412769973	131528417	0	0
ReqAndReadyImplyGrant_A	412769973	131528417	0	0
ReqImpliesValid_A	412769973	137725296	0	0
ValidKnown_A	412769973	411943476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131528417	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131528417	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131528417	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	48253196	0	0
T1	1104	128	0	0
T2	3261	425	0	0
T3	8371	450	0	0
T10	643	136	0	0
T11	127622	2982	0	0
T14	5729	256	0	0
T15	2180	128	0	0
T16	3921	670	0	0
T17	1748	128	0	0
T18	567627	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	137725296	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131528417	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	131528417	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	137725296	0	0
T1	1104	32	0	0
T2	3261	566	0	0
T3	8371	4778	0	0
T10	643	34	0	0
T11	127622	0	0	0
T14	5729	2924	0	0
T15	2180	470	0	0
T16	3921	198	0	0
T17	1748	32	0	0
T18	567627	289347	0	0
T55	0	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T14,T15
1	0	Covered	T14,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T4,T5
1	0	Covered	T1,T14,T15
1	1	Covered	T14,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T4,T5
1	1	Covered	T1,T14,T15

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T4,T5
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412769973	411943476	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	412769973	101305737	0	0
GntImpliesValid_A	412769973	101305737	0	0
GrantKnown_A	412769973	411943476	0	0
IdxKnown_A	412769973	411943476	0	0
IndexIsCorrect_A	412769973	101305737	0	0
NoReadyValidNoGrant_A	412769973	43067173	0	0
Priority_A	412769973	107362428	0	0
ReadyAndValidImplyGrant_A	412769973	101305737	0	0
ReqAndReadyImplyGrant_A	412769973	101305737	0	0
ReqImpliesValid_A	412769973	107362428	0	0
ValidKnown_A	412769973	411943476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	43067173	0	0
T4	108005	41989	0	0
T5	0	41015	0	0
T6	0	2667	0	0
T10	643	0	0	0
T11	127622	1421	0	0
T14	5729	484	0	0
T15	2180	31	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T21	0	150	0	0
T24	384186	4663	0	0
T26	0	1650	0	0
T30	0	25502	0	0
T55	2512	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	107362428	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	16311	0	0
T5	0	15382	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	107362428	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	16311	0	0
T5	0	15382	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T14,T15
1	0	Covered	T14,T4,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T4,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T14,T4,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T4,T5
1	0	Covered	T1,T14,T15
1	1	Covered	T14,T4,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T4,T5
1	1	Covered	T1,T14,T15

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T4,T5
1	1	Covered	T1,T14,T15

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T4,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T14,T4,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412769973	411943476	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	412769973	101305737	0	0
GntImpliesValid_A	412769973	101305737	0	0
GrantKnown_A	412769973	411943476	0	0
IdxKnown_A	412769973	411943476	0	0
IndexIsCorrect_A	412769973	101305737	0	0
NoReadyValidNoGrant_A	412769973	43067173	0	0
Priority_A	412769973	107362428	0	0
ReadyAndValidImplyGrant_A	412769973	101305737	0	0
ReqAndReadyImplyGrant_A	412769973	101305737	0	0
ReqImpliesValid_A	412769973	107362428	0	0
ValidKnown_A	412769973	411943476	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	43067173	0	0
T4	108005	41989	0	0
T5	0	41015	0	0
T6	0	2667	0	0
T10	643	0	0	0
T11	127622	1421	0	0
T14	5729	484	0	0
T15	2180	31	0	0
T16	3921	0	0	0
T17	1748	0	0	0
T18	567627	0	0	0
T21	0	150	0	0
T24	384186	4663	0	0
T26	0	1650	0	0
T30	0	25502	0	0
T55	2512	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	107362428	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	16311	0	0
T5	0	15382	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	101305737	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	15199	0	0
T5	0	14467	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	107362428	0	0
T1	1104	119	0	0
T2	3261	0	0	0
T3	8371	0	0	0
T4	0	16311	0	0
T5	0	15382	0	0
T10	643	0	0	0
T11	127622	0	0	0
T14	5729	204	0	0
T15	2180	464	0	0
T16	3921	0	0	0
T17	1748	444	0	0
T18	567627	275608	0	0
T21	0	198680	0	0
T24	0	56962	0	0
T26	0	25364	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412769973	411943476	0	0
T1	1104	1015	0	0
T2	3261	3096	0	0
T3	8371	8187	0	0
T10	643	586	0	0
T11	127622	102378	0	0
T14	5729	5573	0	0
T15	2180	2117	0	0
T16	3921	3140	0	0
T17	1748	1693	0	0
T18	567627	567618	0	0