Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26366000	1		T1	10474		T2	129		T3	797
full_word	7958109	1		T1	12811		T2	73		T3	582

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34323809	1		T1	23285		T2	202		T3	1379
auto[TlIntgErrCmd]	95	1		T63	8		T193	3		T232	1
auto[TlIntgErrData]	113	1		T63	7		T193	4		T232	4
auto[TlIntgErrBoth]	92	1		T63	5		T193	3		T232	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29800042	1		T1	16533		T2	58		T3	970
auto[1]	4524067	1		T1	6752		T2	144		T3	409

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25699923	1		T1	10200		T2	57		T3	742
auto[TlIntgErrNone]	partial	auto[1]	665800	1		T1	274		T2	72		T3	55
auto[TlIntgErrNone]	full_word	auto[0]	4099992	1		T1	6333		T2	1		T3	228
auto[TlIntgErrNone]	full_word	auto[1]	3858094	1		T1	6478		T2	72		T3	354
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T63	3		T193	1		T232	1
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T63	5		T193	1		T276	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T275	1		T355	1		T354	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T193	1		T349	1		T277	1
auto[TlIntgErrData]	partial	auto[0]	43	1		T63	2		T193	1		T232	1
auto[TlIntgErrData]	partial	auto[1]	62	1		T63	5		T193	3		T232	3
auto[TlIntgErrData]	full_word	auto[0]	3	1		T276	1		T275	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T276	1		T270	1		T351	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1		T63	1		T193	1		T232	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T63	4		T193	2		T232	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T277	2		T353	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T232	1		T351	1		T352	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23760	1		T179	962		T62	516		T63	15
full_word	4462970	1		T3	10		T4	16		T6	16625

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4486464	1		T3	10		T4	16		T6	16625
auto[TlIntgErrCmd]	86	1		T63	4		T193	3		T232	2
auto[TlIntgErrData]	87	1		T63	10		T193	3		T232	1
auto[TlIntgErrBoth]	93	1		T63	2		T193	2		T232	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4457041	1		T3	10		T4	16		T6	16625
auto[1]	29689	1		T179	1011		T62	655		T63	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1607	1		T179	69		T62	17		T192	156
auto[TlIntgErrNone]	partial	auto[1]	21910	1		T179	893		T62	499		T192	1476
auto[TlIntgErrNone]	full_word	auto[0]	4455316	1		T3	10		T4	16		T6	16625
auto[TlIntgErrNone]	full_word	auto[1]	7631	1		T179	118		T62	156		T192	618
auto[TlIntgErrCmd]	partial	auto[0]	32	1		T63	3		T193	1		T232	1
auto[TlIntgErrCmd]	partial	auto[1]	46	1		T63	1		T193	2		T232	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T349	1		T355	1		T350	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T276	1		T356	1		T274	1
auto[TlIntgErrData]	partial	auto[0]	45	1		T63	5		T193	2		T232	1
auto[TlIntgErrData]	partial	auto[1]	32	1		T63	4		T276	1		T270	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T63	1		T193	1		T276	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T275	1		T357	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T63	1		T232	3		T276	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T63	1		T193	2		T232	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T276	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T276	2		T275	2		-	-