Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T4,T6

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1680652800	1677224308	0	0
CheckNGreaterZero_A	4248	4248	0	0
GntImpliesReady_A	1680652800	454095735	0	0
GntImpliesValid_A	1680652800	454095735	0	0
GrantKnown_A	1680652800	1677224308	0	0
IdxKnown_A	1680652800	1677224308	0	0
IndexIsCorrect_A	1680652800	454095735	0	0
NoReadyValidNoGrant_A	1680652800	180684120	0	0
Priority_A	1680652800	478144413	0	0
ReadyAndValidImplyGrant_A	1680652800	454095735	0	0
ReqAndReadyImplyGrant_A	1680652800	454095735	0	0
ReqImpliesValid_A	1680652800	478144413	0	0
ValidKnown_A	1680652800	1677224308	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	1677224308	0	0
T1	216092	215852	0	0
T2	14652	14264	0	0
T3	13868	13272	0	0
T4	41072	40488	0	0
T5	577076	473336	0	0
T6	3296660	3296084	0	0
T7	1225744	1225376	0	0
T16	1042112	1041892	0	0
T17	21252	20648	0	0
T18	7572	7000	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4248	4248	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	454095735	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	58860	0	0
T7	1225744	374552	0	0
T8	0	118510	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	454095735	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	58860	0	0
T7	1225744	374552	0	0
T8	0	118510	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	1677224308	0	0
T1	216092	215852	0	0
T2	14652	14264	0	0
T3	13868	13272	0	0
T4	41072	40488	0	0
T5	577076	473336	0	0
T6	3296660	3296084	0	0
T7	1225744	1225376	0	0
T16	1042112	1041892	0	0
T17	21252	20648	0	0
T18	7572	7000	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	1677224308	0	0
T1	216092	215852	0	0
T2	14652	14264	0	0
T3	13868	13272	0	0
T4	41072	40488	0	0
T5	577076	473336	0	0
T6	3296660	3296084	0	0
T7	1225744	1225376	0	0
T16	1042112	1041892	0	0
T17	21252	20648	0	0
T18	7572	7000	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	454095735	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	58860	0	0
T7	1225744	374552	0	0
T8	0	118510	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	180684120	0	0
T1	108046	2688	0	0
T2	7326	256	0	0
T3	6934	1556	0	0
T4	41072	1684	0	0
T5	577076	0	0	0
T6	3296660	1989236	0	0
T7	1225744	238322	0	0
T8	0	79258	0	0
T12	2248	0	0	0
T13	760600	1048576	0	0
T16	1042112	3064	0	0
T17	21252	1780	0	0
T18	7572	512	0	0
T20	0	384	0	0
T25	0	1052160	0	0
T59	196160	7628	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	478144413	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	482188	0	0
T7	1225744	440914	0	0
T8	0	148036	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	454095735	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	58860	0	0
T7	1225744	374552	0	0
T8	0	118510	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	454095735	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	58860	0	0
T7	1225744	374552	0	0
T8	0	118510	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	478144413	0	0
T1	108046	29184	0	0
T2	7326	64	0	0
T3	6934	542	0	0
T4	41072	15164	0	0
T5	577076	0	0	0
T6	3296660	482188	0	0
T7	1225744	440914	0	0
T8	0	148036	0	0
T12	2248	0	0	0
T13	760600	255794	0	0
T16	1042112	454464	0	0
T17	21252	670	0	0
T18	7572	148	0	0
T59	196160	124070	0	0
T60	0	220208	0	0
T72	0	48	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1680652800	1677224308	0	0
T1	216092	215852	0	0
T2	14652	14264	0	0
T3	13868	13272	0	0
T4	41072	40488	0	0
T5	577076	473336	0	0
T6	3296660	3296084	0	0
T7	1225744	1225376	0	0
T16	1042112	1041892	0	0
T17	21252	20648	0	0
T18	7572	7000	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420163200	419306077	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	420163200	120178397	0	0
GntImpliesValid_A	420163200	120178397	0	0
GrantKnown_A	420163200	419306077	0	0
IdxKnown_A	420163200	419306077	0	0
IndexIsCorrect_A	420163200	120178397	0	0
NoReadyValidNoGrant_A	420163200	46644813	0	0
Priority_A	420163200	126354706	0	0
ReadyAndValidImplyGrant_A	420163200	120178397	0	0
ReqAndReadyImplyGrant_A	420163200	120178397	0	0
ReqImpliesValid_A	420163200	126354706	0	0
ValidKnown_A	420163200	419306077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120178397	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120178397	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120178397	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	46644813	0	0
T1	54023	1344	0	0
T2	3663	128	0	0
T3	3467	778	0	0
T4	10268	256	0	0
T5	144269	0	0	0
T6	824165	462641	0	0
T7	306436	71721	0	0
T16	260528	962	0	0
T17	5313	256	0	0
T18	1893	256	0	0
T59	0	1858	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	126354706	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	111572	0	0
T7	306436	95904	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120178397	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120178397	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	126354706	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	111572	0	0
T7	306436	95904	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T6,T7
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T6,T7

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T6,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T6,T7

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420163200	419306077	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	420163200	120013300	0	0
GntImpliesValid_A	420163200	120013300	0	0
GrantKnown_A	420163200	419306077	0	0
IdxKnown_A	420163200	419306077	0	0
IndexIsCorrect_A	420163200	120013300	0	0
NoReadyValidNoGrant_A	420163200	46644815	0	0
Priority_A	420163200	126189607	0	0
ReadyAndValidImplyGrant_A	420163200	120013300	0	0
ReqAndReadyImplyGrant_A	420163200	120013300	0	0
ReqImpliesValid_A	420163200	126189607	0	0
ValidKnown_A	420163200	419306077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120013300	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120013300	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120013300	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	46644815	0	0
T1	54023	1344	0	0
T2	3663	128	0	0
T3	3467	778	0	0
T4	10268	256	0	0
T5	144269	0	0	0
T6	824165	462641	0	0
T7	306436	71721	0	0
T16	260528	962	0	0
T17	5313	256	0	0
T18	1893	256	0	0
T59	0	1858	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	126189607	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	111572	0	0
T7	306436	95904	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120013300	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	120013300	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	13334	0	0
T7	306436	80566	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	126189607	0	0
T1	54023	14592	0	0
T2	3663	32	0	0
T3	3467	271	0	0
T4	10268	7344	0	0
T5	144269	0	0	0
T6	824165	111572	0	0
T7	306436	95904	0	0
T16	260528	212109	0	0
T17	5313	64	0	0
T18	1893	74	0	0
T59	0	28817	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T6
1	0	Covered	T4,T6,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T16,T6
1	1	Covered	T4,T6,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T16,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T16,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420163200	419306077	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	420163200	106952019	0	0
GntImpliesValid_A	420163200	106952019	0	0
GrantKnown_A	420163200	419306077	0	0
IdxKnown_A	420163200	419306077	0	0
IndexIsCorrect_A	420163200	106952019	0	0
NoReadyValidNoGrant_A	420163200	43697246	0	0
Priority_A	420163200	112800050	0	0
ReadyAndValidImplyGrant_A	420163200	106952019	0	0
ReqAndReadyImplyGrant_A	420163200	106952019	0	0
ReqImpliesValid_A	420163200	112800050	0	0
ValidKnown_A	420163200	419306077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	43697246	0	0
T4	10268	586	0	0
T5	144269	0	0	0
T6	824165	531977	0	0
T7	306436	47440	0	0
T8	0	39629	0	0
T12	1124	0	0	0
T13	380300	524288	0	0
T16	260528	570	0	0
T17	5313	634	0	0
T18	1893	0	0	0
T20	0	192	0	0
T25	0	526080	0	0
T59	98080	1956	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	112800050	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	129522	0	0
T7	306436	124553	0	0
T8	0	74018	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	112800050	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	129522	0	0
T7	306436	124553	0	0
T8	0	74018	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T16,T6
1	0	Covered	T4,T6,T17

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T4,T6,T17
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T17
1	0	Covered	T4,T16,T6
1	1	Covered	T4,T6,T17

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T16,T6

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T17
1	1	Covered	T4,T16,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T17

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T6,T17

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420163200	419306077	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	420163200	106952019	0	0
GntImpliesValid_A	420163200	106952019	0	0
GrantKnown_A	420163200	419306077	0	0
IdxKnown_A	420163200	419306077	0	0
IndexIsCorrect_A	420163200	106952019	0	0
NoReadyValidNoGrant_A	420163200	43697246	0	0
Priority_A	420163200	112800050	0	0
ReadyAndValidImplyGrant_A	420163200	106952019	0	0
ReqAndReadyImplyGrant_A	420163200	106952019	0	0
ReqImpliesValid_A	420163200	112800050	0	0
ValidKnown_A	420163200	419306077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	43697246	0	0
T4	10268	586	0	0
T5	144269	0	0	0
T6	824165	531977	0	0
T7	306436	47440	0	0
T8	0	39629	0	0
T12	1124	0	0	0
T13	380300	524288	0	0
T16	260528	570	0	0
T17	5313	634	0	0
T18	1893	0	0	0
T20	0	192	0	0
T25	0	526080	0	0
T59	98080	1956	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	112800050	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	129522	0	0
T7	306436	124553	0	0
T8	0	74018	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	106952019	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	16096	0	0
T7	306436	106710	0	0
T8	0	59255	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	112800050	0	0
T4	10268	238	0	0
T5	144269	0	0	0
T6	824165	129522	0	0
T7	306436	124553	0	0
T8	0	74018	0	0
T12	1124	0	0	0
T13	380300	127897	0	0
T16	260528	15123	0	0
T17	5313	271	0	0
T18	1893	0	0	0
T59	98080	33218	0	0
T60	0	110104	0	0
T72	0	24	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420163200	419306077	0	0
T1	54023	53963	0	0
T2	3663	3566	0	0
T3	3467	3318	0	0
T4	10268	10122	0	0
T5	144269	118334	0	0
T6	824165	824021	0	0
T7	306436	306344	0	0
T16	260528	260473	0	0
T17	5313	5162	0	0
T18	1893	1750	0	0