Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27887159	1		T1	926		T2	7239		T3	156
full_word	7923136	1		T1	2693		T2	116		T3	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	35809965	1		T1	3619		T2	7355		T3	158
auto[TlIntgErrCmd]	113	1		T38	3		T39	2		T40	3
auto[TlIntgErrData]	107	1		T38	5		T39	3		T40	4
auto[TlIntgErrBoth]	110	1		T38	2		T39	5		T40	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31271007	1		T1	1314		T2	7248		T3	149
auto[1]	4539288	1		T1	2305		T2	107		T3	9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	27222412	1		T1	699		T2	7225		T3	149
auto[TlIntgErrNone]	partial	auto[1]	664443	1		T1	227		T2	14		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	4048453	1		T1	615		T2	23		T4	2623
auto[TlIntgErrNone]	full_word	auto[1]	3874657	1		T1	2078		T2	93		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	43	1		T38	1		T39	1		T40	3
auto[TlIntgErrCmd]	partial	auto[1]	55	1		T38	2		T39	1		T199	4
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T294	1		T367	1		T371	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T228	2		T367	1		T259	3
auto[TlIntgErrData]	partial	auto[0]	45	1		T38	1		T39	1		T199	4
auto[TlIntgErrData]	partial	auto[1]	56	1		T38	4		T39	2		T40	4
auto[TlIntgErrData]	full_word	auto[0]	3	1		T372	3		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1		T294	1		T259	1		T370	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1		T38	1		T39	2		T40	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1		T38	1		T39	2		T40	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T296	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T39	1		T227	1		T373	2

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	19740	1		T38	9		T39	7		T40	10
full_word	4468237	1		T1	416		T5	13		T20	7

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4487669	1		T1	416		T5	13		T20	7
auto[TlIntgErrCmd]	99	1		T38	4		T39	3		T40	2
auto[TlIntgErrData]	112	1		T38	2		T39	2		T40	4
auto[TlIntgErrBoth]	97	1		T38	4		T39	4		T40	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4463593	1		T1	416		T5	13		T20	7
auto[1]	24384	1		T38	9		T39	4		T40	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1233	1		T193	1		T194	77		T195	48
auto[TlIntgErrNone]	partial	auto[1]	18235	1		T193	30		T194	927		T195	1272
auto[TlIntgErrNone]	full_word	auto[0]	4462245	1		T1	416		T5	13		T20	7
auto[TlIntgErrNone]	full_word	auto[1]	5956	1		T193	14		T194	416		T195	300
auto[TlIntgErrCmd]	partial	auto[0]	22	1		T39	1		T40	1		T199	2
auto[TlIntgErrCmd]	partial	auto[1]	65	1		T38	4		T39	2		T40	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T294	1		T374	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1		T199	1		T228	2		T230	2
auto[TlIntgErrData]	partial	auto[0]	47	1		T39	1		T40	1		T199	2
auto[TlIntgErrData]	partial	auto[1]	52	1		T38	2		T40	3		T199	2
auto[TlIntgErrData]	full_word	auto[0]	6	1		T39	1		T198	1		T373	1
auto[TlIntgErrData]	full_word	auto[1]	7	1		T228	1		T371	1		T264	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T38	1		T39	2		T40	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T38	2		T39	1		T40	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T230	1		T259	1		T373	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T38	1		T39	1		T227	1