Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1571682320	1568332696	0	0
CheckNGreaterZero_A	4252	4252	0	0
GntImpliesReady_A	1571682320	462279083	0	0
GntImpliesValid_A	1571682320	462279083	0	0
GrantKnown_A	1571682320	1568332696	0	0
IdxKnown_A	1571682320	1568332696	0	0
IndexIsCorrect_A	1571682320	462279083	0	0
NoReadyValidNoGrant_A	1571682320	181518271	0	0
Priority_A	1571682320	486615274	0	0
ReadyAndValidImplyGrant_A	1571682320	462279083	0	0
ReqAndReadyImplyGrant_A	1571682320	462279083	0	0
ReqImpliesValid_A	1571682320	486615274	0	0
ValidKnown_A	1571682320	1568332696	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	1568332696	0	0
T1	125420	125024	0	0
T2	272968	272600	0	0
T3	15720	13204	0	0
T4	833256	832864	0	0
T5	25184	24624	0	0
T6	7716	7512	0	0
T12	5328	4956	0	0
T17	485508	485216	0	0
T18	5456	4844	0	0
T19	646424	646180	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4252	4252	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T12	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	462279083	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	44	0	0
T8	0	197484	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	271586	0	0
T58	0	20114	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	462279083	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	44	0	0
T8	0	197484	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	271586	0	0
T58	0	20114	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	1568332696	0	0
T1	125420	125024	0	0
T2	272968	272600	0	0
T3	15720	13204	0	0
T4	833256	832864	0	0
T5	25184	24624	0	0
T6	7716	7512	0	0
T12	5328	4956	0	0
T17	485508	485216	0	0
T18	5456	4844	0	0
T19	646424	646180	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	1568332696	0	0
T1	125420	125024	0	0
T2	272968	272600	0	0
T3	15720	13204	0	0
T4	833256	832864	0	0
T5	25184	24624	0	0
T6	7716	7512	0	0
T12	5328	4956	0	0
T17	485508	485216	0	0
T18	5456	4844	0	0
T19	646424	646180	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	462279083	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	44	0	0
T8	0	197484	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	271586	0	0
T58	0	20114	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	181518271	0	0
T1	125420	3050	0	0
T2	272968	316	0	0
T3	15720	1588	0	0
T4	833256	7384	0	0
T5	25184	1746	0	0
T6	7716	256	0	0
T7	0	44	0	0
T8	0	84406	0	0
T12	5328	256	0	0
T17	485508	2688	0	0
T18	5456	512	0	0
T19	646424	3200	0	0
T21	0	44	0	0
T33	0	159154	0	0
T53	0	3396	0	0
T58	0	26216	0	0
T59	0	806400	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	486615274	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	98	0	0
T8	0	236074	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	304906	0	0
T58	0	25606	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	462279083	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	44	0	0
T8	0	197484	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	271586	0	0
T58	0	20114	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	462279083	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	44	0	0
T8	0	197484	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	271586	0	0
T58	0	20114	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	486615274	0	0
T1	125420	1900	0	0
T2	272968	131702	0	0
T3	15720	422	0	0
T4	833256	88042	0	0
T5	25184	3510	0	0
T6	7716	952	0	0
T7	0	98	0	0
T8	0	236074	0	0
T12	5328	584	0	0
T17	485508	1608	0	0
T18	5456	260	0	0
T19	646424	28960	0	0
T21	0	818	0	0
T22	0	374862	0	0
T33	0	304906	0	0
T58	0	25606	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1571682320	1568332696	0	0
T1	125420	125024	0	0
T2	272968	272600	0	0
T3	15720	13204	0	0
T4	833256	832864	0	0
T5	25184	24624	0	0
T6	7716	7512	0	0
T12	5328	4956	0	0
T17	485508	485216	0	0
T18	5456	4844	0	0
T19	646424	646180	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392920580	392083174	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392920580	118215447	0	0
GntImpliesValid_A	392920580	118215447	0	0
GrantKnown_A	392920580	392083174	0	0
IdxKnown_A	392920580	392083174	0	0
IndexIsCorrect_A	392920580	118215447	0	0
NoReadyValidNoGrant_A	392920580	46470564	0	0
Priority_A	392920580	124418977	0	0
ReadyAndValidImplyGrant_A	392920580	118215447	0	0
ReqAndReadyImplyGrant_A	392920580	118215447	0	0
ReqImpliesValid_A	392920580	124418977	0	0
ValidKnown_A	392920580	392083174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118215447	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118215447	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118215447	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	46470564	0	0
T1	31355	836	0	0
T2	68242	130	0	0
T3	3930	794	0	0
T4	208314	1844	0	0
T5	6296	873	0	0
T6	1929	128	0	0
T12	1332	128	0	0
T17	121377	1344	0	0
T18	1364	256	0	0
T19	161606	1600	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	124418977	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118215447	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118215447	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	124418977	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T20,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T7
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392920580	392083174	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392920580	118089850	0	0
GntImpliesValid_A	392920580	118089850	0	0
GrantKnown_A	392920580	392083174	0	0
IdxKnown_A	392920580	392083174	0	0
IndexIsCorrect_A	392920580	118089850	0	0
NoReadyValidNoGrant_A	392920580	46470565	0	0
Priority_A	392920580	124293379	0	0
ReadyAndValidImplyGrant_A	392920580	118089850	0	0
ReqAndReadyImplyGrant_A	392920580	118089850	0	0
ReqImpliesValid_A	392920580	124293379	0	0
ValidKnown_A	392920580	392083174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118089850	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118089850	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118089850	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	46470565	0	0
T1	31355	836	0	0
T2	68242	130	0	0
T3	3930	794	0	0
T4	208314	1844	0	0
T5	6296	873	0	0
T6	1929	128	0	0
T12	1332	128	0	0
T17	121377	1344	0	0
T18	1364	256	0	0
T19	161606	1600	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	124293379	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118089850	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118089850	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	124293379	0	0
T1	31355	500	0	0
T2	68242	293	0	0
T3	3930	211	0	0
T4	208314	21135	0	0
T5	6296	1755	0	0
T6	1929	32	0	0
T12	1332	292	0	0
T17	121377	804	0	0
T18	1364	130	0	0
T19	161606	14480	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T33
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392920580	392083174	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392920580	112986893	0	0
GntImpliesValid_A	392920580	112986893	0	0
GrantKnown_A	392920580	392083174	0	0
IdxKnown_A	392920580	392083174	0	0
IndexIsCorrect_A	392920580	112986893	0	0
NoReadyValidNoGrant_A	392920580	44288571	0	0
Priority_A	392920580	118951459	0	0
ReadyAndValidImplyGrant_A	392920580	112986893	0	0
ReqAndReadyImplyGrant_A	392920580	112986893	0	0
ReqImpliesValid_A	392920580	118951459	0	0
ValidKnown_A	392920580	392083174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	44288571	0	0
T1	31355	689	0	0
T2	68242	28	0	0
T3	3930	0	0	0
T4	208314	1848	0	0
T5	6296	0	0	0
T6	1929	0	0	0
T7	0	22	0	0
T8	0	42203	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	22	0	0
T33	0	79577	0	0
T53	0	1698	0	0
T58	0	13108	0	0
T59	0	403200	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118951459	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	49	0	0
T8	0	118037	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	152453	0	0
T58	0	12803	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118951459	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	49	0	0
T8	0	118037	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	152453	0	0
T58	0	12803	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T33
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T33
1	1	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	392920580	392083174	0	0
CheckNGreaterZero_A	1063	1063	0	0
GntImpliesReady_A	392920580	112986893	0	0
GntImpliesValid_A	392920580	112986893	0	0
GrantKnown_A	392920580	392083174	0	0
IdxKnown_A	392920580	392083174	0	0
IndexIsCorrect_A	392920580	112986893	0	0
NoReadyValidNoGrant_A	392920580	44288571	0	0
Priority_A	392920580	118951459	0	0
ReadyAndValidImplyGrant_A	392920580	112986893	0	0
ReqAndReadyImplyGrant_A	392920580	112986893	0	0
ReqImpliesValid_A	392920580	118951459	0	0
ValidKnown_A	392920580	392083174	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	44288571	0	0
T1	31355	689	0	0
T2	68242	28	0	0
T3	3930	0	0	0
T4	208314	1848	0	0
T5	6296	0	0	0
T6	1929	0	0	0
T7	0	22	0	0
T8	0	42203	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	22	0	0
T33	0	79577	0	0
T53	0	1698	0	0
T58	0	13108	0	0
T59	0	403200	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118951459	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	49	0	0
T8	0	118037	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	152453	0	0
T58	0	12803	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	112986893	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	22	0	0
T8	0	98742	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	135793	0	0
T58	0	10057	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	118951459	0	0
T1	31355	450	0	0
T2	68242	65558	0	0
T3	3930	0	0	0
T4	208314	22886	0	0
T5	6296	0	0	0
T6	1929	444	0	0
T7	0	49	0	0
T8	0	118037	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	409	0	0
T22	0	187431	0	0
T33	0	152453	0	0
T58	0	12803	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0