Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T114,T219,T220
1	0	Covered	T114,T219,T220

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T114,T219,T220

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T114,T219,T220
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T18,T8

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T18,T8,T21

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T18,T8,T21

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T18,T8

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T5,T18,T8

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T19,T22
1	Covered	T5,T6,T18

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T18
1	1	Covered	T5,T6,T18

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T18
1	1	Covered	T5,T6,T18

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T6,T18
StCalcMask	237	Covered	T5,T6,T18
StCalcPlainEcc	215	Covered	T4,T5,T6
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T6
StPostPack	218	Covered	T5,T18,T8
StPrePack	195	Covered	T18,T8,T21
StReqFlash	237	Covered	T4,T5,T6
StScrambleData	244	Covered	T5,T6,T18
StWaitFlash	270	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T6,T18
StCalcMask->StScrambleData	244	Covered	T5,T6,T18
StCalcPlainEcc->StCalcMask	237	Covered	T5,T6,T18
StCalcPlainEcc->StReqFlash	237	Covered	T4,T19,T22
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T4,T5,T6
StIdle->StPrePack	195	Covered	T18,T8,T21
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T6
StPackData->StPostPack	218	Covered	T5,T18,T8
StPostPack->StCalcPlainEcc	231	Covered	T5,T18,T8
StPrePack->StPackData	205	Covered	T18,T8,T21
StReqFlash->StIdle	273	Covered	T4,T5,T6
StReqFlash->StWaitFlash	270	Covered	T4,T5,T6
StScrambleData->StCalcEcc	252	Covered	T5,T6,T18
StWaitFlash->StIdle	280	Covered	T4,T5,T6

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T8,T21
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T8,T21
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T8
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T18,T8
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T6,T18
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T19,T22
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T6,T18
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T6,T18
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T6,T18
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T6,T18
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T6
0	0	1	-	-	Covered	T5,T6,T18
0	0	0	1	-	Covered	T5,T6,T18
0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	785841160	2404477	0	0
PostPackRule_A	785841160	30145	0	0
PrePackRule_A	785841160	15411	0	0
WidthCheck_A	2126	2126	0	0
u_state_regs_A	785841160	784166348	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785841160	2404477	0	0
T4	416628	100	0	0
T5	12592	9	0	0
T6	3858	1	0	0
T7	1092	0	0	0
T8	0	1457	0	0
T12	2664	0	0	0
T17	242754	0	0	0
T18	2728	0	0	0
T19	323212	32	0	0
T20	9914	0	0	0
T21	0	9	0	0
T22	978564	1099	0	0
T24	0	1	0	0
T33	0	1170	0	0
T53	0	100	0	0
T59	0	8608	0	0
T64	0	8	0	0
T77	0	292	0	0
T97	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785841160	30145	0	0
T5	6296	3	0	0
T6	1929	0	0	0
T7	546	0	0	0
T8	711920	408	0	0
T12	1332	0	0	0
T13	568	0	0	0
T17	121377	0	0	0
T18	1364	1	0	0
T19	161606	0	0	0
T20	4957	0	0	0
T21	13363	6	0	0
T22	489282	0	0	0
T24	0	1	0	0
T33	324966	418	0	0
T41	0	12	0	0
T43	0	129	0	0
T44	0	134	0	0
T58	35073	0	0	0
T59	489122	0	0	0
T64	4865	0	0	0
T65	1088	0	0	0
T69	0	1	0	0
T77	389986	0	0	0
T92	0	334	0	0
T96	1473	0	0	0
T155	0	34	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785841160	15411	0	0
T7	546	0	0	0
T8	711920	266	0	0
T13	1136	0	0	0
T18	1364	1	0	0
T19	161606	0	0	0
T20	4957	0	0	0
T21	26726	5	0	0
T22	489282	0	0	0
T24	0	1	0	0
T33	649932	228	0	0
T41	0	13	0	0
T43	0	53	0	0
T44	0	103	0	0
T58	70146	0	0	0
T59	489122	0	0	0
T64	4865	0	0	0
T65	1088	0	0	0
T69	0	6	0	0
T77	389986	0	0	0
T92	0	166	0	0
T96	1473	0	0	0
T155	0	28	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2126	2126	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T12	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	785841160	784166348	0	0
T1	62710	62512	0	0
T2	136484	136300	0	0
T3	7860	6602	0	0
T4	416628	416432	0	0
T5	12592	12312	0	0
T6	3858	3756	0	0
T12	2664	2478	0	0
T17	242754	242608	0	0
T18	2728	2422	0	0
T19	323212	323090	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T114,T219,T220
1	0	Covered	T114,T219,T220

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T114,T219,T220

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T114,T219,T220
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T5,T18,T8

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18
1	1	Covered	T4,T5,T18

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T18

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T18,T8,T21

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T18,T8,T21

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T4,T5,T18
1	1	Covered	T4,T5,T18

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T4,T5,T18

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T19
1	0	Covered	T4,T5,T18
1	1	Covered	T5,T18,T8

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T5,T18,T8

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T19,T22
1	Covered	T5,T18,T33

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T18
1	Covered	T4,T5,T18

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T19
1	Covered	T4,T5,T18

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T18
1	1	Covered	T4,T5,T18

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T18,T33
1	1	Covered	T5,T18,T33

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T18,T33
1	1	Covered	T5,T18,T33

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T18
1	1	0	Covered	T4,T5,T18
1	1	1	Covered	T4,T5,T19

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T19

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T5,T18,T33
StCalcMask	237	Covered	T5,T18,T33
StCalcPlainEcc	215	Covered	T4,T5,T18
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T18
StPostPack	218	Covered	T5,T18,T8
StPrePack	195	Covered	T18,T8,T21
StReqFlash	237	Covered	T4,T5,T18
StScrambleData	244	Covered	T5,T18,T33
StWaitFlash	270	Covered	T4,T5,T18

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T5,T18,T33
StCalcMask->StScrambleData	244	Covered	T5,T18,T33
StCalcPlainEcc->StCalcMask	237	Covered	T5,T18,T33
StCalcPlainEcc->StReqFlash	237	Covered	T4,T19,T22
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T4,T5,T18
StIdle->StPrePack	195	Covered	T18,T8,T21
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T18
StPackData->StPostPack	218	Covered	T5,T18,T8
StPostPack->StCalcPlainEcc	231	Covered	T5,T18,T8
StPrePack->StPackData	205	Covered	T18,T8,T21
StReqFlash->StIdle	273	Covered	T4,T5,T18
StReqFlash->StWaitFlash	270	Covered	T4,T5,T18
StScrambleData->StCalcEcc	252	Covered	T5,T18,T33
StWaitFlash->StIdle	280	Covered	T4,T5,T18

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T19
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T18
0	0	1	Covered	T4,T5,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T8,T21
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T8,T21
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T8
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T5,T18,T8
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T5,T18,T33
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T19,T22
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T5,T18,T33
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T5,T18,T33
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T18,T33
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T5,T18,T33
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T33
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T18
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T19
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T19
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T18
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T18
0	0	1	-	-	Covered	T5,T18,T33
0	0	0	1	-	Covered	T5,T18,T33
0	0	0	0	1	Covered	T4,T5,T18
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T18
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	392920580	1208010	0	0
PostPackRule_A	392920580	17047	0	0
PrePackRule_A	392920580	8845	0	0
WidthCheck_A	1063	1063	0	0
u_state_regs_A	392920580	392083174	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	1208010	0	0
T4	208314	48	0	0
T5	6296	9	0	0
T6	1929	0	0	0
T7	546	0	0	0
T8	0	946	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	32	0	0
T20	4957	0	0	0
T21	0	7	0	0
T22	489282	676	0	0
T33	0	350	0	0
T53	0	53	0	0
T64	0	8	0	0
T77	0	292	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	17047	0	0
T5	6296	3	0	0
T6	1929	0	0	0
T7	546	0	0	0
T8	355960	305	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	1	0	0
T19	161606	0	0	0
T20	4957	0	0	0
T21	0	5	0	0
T22	489282	0	0	0
T33	0	182	0	0
T41	0	6	0	0
T43	0	123	0	0
T44	0	67	0	0
T92	0	202	0	0
T155	0	10	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	8845	0	0
T7	546	0	0	0
T8	355960	195	0	0
T13	568	0	0	0
T18	1364	1	0	0
T19	161606	0	0	0
T20	4957	0	0	0
T21	13363	3	0	0
T22	489282	0	0	0
T33	324966	75	0	0
T41	0	3	0	0
T43	0	52	0	0
T44	0	52	0	0
T58	35073	0	0	0
T69	0	4	0	0
T92	0	77	0	0
T155	0	12	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T22

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T22

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T221,T171
1	0	Covered	T9,T221,T171

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T22
1	1	Covered	T9,T221,T171

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T221,T171
1	0	Covered	T1,T2,T4

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T22

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T8,T21,T33

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T22
1	0	Covered	T4,T6,T22
1	1	Covered	T4,T6,T22

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T22

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T22
1	1	Covered	T8,T21,T33

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T8,T21,T33

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T22
1	0	Covered	T4,T6,T22
1	1	Covered	T4,T6,T22

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T4,T6,T22

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T22
1	0	Covered	T4,T6,T22
1	1	Covered	T8,T21,T33

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T14
1	Covered	T8,T21,T33

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T22,T8
1	Covered	T6,T33,T97

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T4,T6,T22

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T6,T22
1	Covered	T4,T6,T22

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T6,T22
1	1	Covered	T4,T6,T22

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T7,T33,T23
1	0	Covered	T6,T33,T97
1	1	Covered	T6,T33,T97

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T33,T23,T24
1	0	Covered	T6,T33,T97
1	1	Covered	T6,T33,T97

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T22
1	1	0	Covered	T4,T6,T22
1	1	1	Covered	T4,T6,T22

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T6,T22

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T6,T33,T97
StCalcMask	237	Covered	T6,T33,T97
StCalcPlainEcc	215	Covered	T4,T6,T22
StDisabled	193	Covered	T3,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T6,T22
StPostPack	218	Covered	T8,T21,T33
StPrePack	195	Covered	T8,T21,T33
StReqFlash	237	Covered	T4,T6,T22
StScrambleData	244	Covered	T6,T33,T97
StWaitFlash	270	Covered	T4,T6,T22

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T6,T33,T97
StCalcMask->StScrambleData	244	Covered	T6,T33,T97
StCalcPlainEcc->StCalcMask	237	Covered	T6,T33,T97
StCalcPlainEcc->StReqFlash	237	Covered	T4,T22,T8
StIdle->StDisabled	193	Covered	T3,T12,T13
StIdle->StPackData	197	Covered	T4,T6,T22
StIdle->StPrePack	195	Covered	T8,T21,T33
StPackData->StCalcPlainEcc	215	Covered	T4,T6,T22
StPackData->StPostPack	218	Covered	T8,T21,T33
StPostPack->StCalcPlainEcc	231	Covered	T8,T21,T33
StPrePack->StPackData	205	Covered	T8,T21,T33
StReqFlash->StIdle	273	Covered	T4,T6,T22
StReqFlash->StWaitFlash	270	Covered	T4,T6,T22
StScrambleData->StCalcEcc	252	Covered	T6,T33,T97
StWaitFlash->StIdle	280	Covered	T4,T6,T22

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T22
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T6,T22
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T6,T22
0	0	1	Covered	T4,T6,T22
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T21,T33
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T22
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T21,T33
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T14
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T22
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T8,T21,T33
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T6,T22
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T6,T22
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T8,T21,T33
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T14
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T6,T33,T97
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T22,T8
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T6,T33,T97
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T6,T33,T97
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T6,T33,T97
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T6,T33,T97
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T33,T97
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T6,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T6,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T6,T22
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T6,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T6,T22
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T6,T22
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T16,T10

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T6,T22
0	0	1	-	-	Covered	T6,T33,T97
0	0	0	1	-	Covered	T6,T33,T97
0	0	0	0	1	Covered	T4,T6,T22
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T6,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	392920580	1196467	0	0
PostPackRule_A	392920580	13098	0	0
PrePackRule_A	392920580	6566	0	0
WidthCheck_A	1063	1063	0	0
u_state_regs_A	392920580	392083174	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	1196467	0	0
T4	208314	52	0	0
T5	6296	0	0	0
T6	1929	1	0	0
T7	546	0	0	0
T8	0	511	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	4957	0	0	0
T21	0	2	0	0
T22	489282	423	0	0
T24	0	1	0	0
T33	0	820	0	0
T53	0	47	0	0
T59	0	8608	0	0
T97	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	13098	0	0
T8	355960	103	0	0
T13	568	0	0	0
T21	13363	1	0	0
T24	0	1	0	0
T33	324966	236	0	0
T41	0	6	0	0
T43	0	6	0	0
T44	0	67	0	0
T58	35073	0	0	0
T59	489122	0	0	0
T64	4865	0	0	0
T65	1088	0	0	0
T69	0	1	0	0
T77	389986	0	0	0
T92	0	132	0	0
T96	1473	0	0	0
T155	0	24	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	6566	0	0
T8	355960	71	0	0
T13	568	0	0	0
T21	13363	2	0	0
T24	0	1	0	0
T33	324966	153	0	0
T41	0	10	0	0
T43	0	1	0	0
T44	0	51	0	0
T58	35073	0	0	0
T59	489122	0	0	0
T64	4865	0	0	0
T65	1088	0	0	0
T69	0	2	0	0
T77	389986	0	0	0
T92	0	89	0	0
T96	1473	0	0	0
T155	0	16	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1063	1063	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0