Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.25	100.00	66.67			84.62	85.71	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	90.30	100.00	80.00			90.91

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	37348399	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	37348399	0	0
T1	31355	3619	0	0
T2	68242	7355	0	0
T3	3930	158	0	0
T4	208314	18732	0	0
T5	6296	2182	0	0
T6	1929	349	0	0
T12	1332	261	0	0
T17	121377	17246	0	0
T18	1364	140	0	0
T19	161606	20126	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	41747249	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	41747249	0	0
T1	31355	3619	0	0
T2	68242	22861	0	0
T3	3930	158	0	0
T4	208314	84250	0	0
T5	6296	2182	0	0
T6	1929	349	0	0
T12	1332	261	0	0
T17	121377	17246	0	0
T18	1364	140	0	0
T19	161606	53176	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	2353845	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	2353845	0	0
T4	208314	1188	0	0
T5	6296	208	0	0
T6	1929	16	0	0
T7	546	0	0	0
T8	0	8267	0	0
T12	1332	0	0	0
T17	121377	2048	0	0
T18	1364	4	0	0
T19	161606	7553	0	0
T20	4957	0	0	0
T21	0	132	0	0
T22	489282	18128	0	0
T33	0	8162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	2764076	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	2764076	0	0
T4	208314	5353	0	0
T5	6296	208	0	0
T6	1929	16	0	0
T7	546	0	0	0
T8	0	8267	0	0
T12	1332	0	0	0
T17	121377	2048	0	0
T18	1364	4	0	0
T19	161606	14272	0	0
T20	4957	0	0	0
T21	0	317	0	0
T22	489282	18128	0	0
T33	0	8162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	4174180	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	4174180	0	0
T1	31355	592	0	0
T2	68242	19	0	0
T3	3930	0	0	0
T4	208314	2376	0	0
T5	6296	220	0	0
T6	1929	0	0	0
T7	0	20	0	0
T8	0	17837	0	0
T12	1332	0	0	0
T17	121377	7168	0	0
T18	1364	0	0	0
T19	161606	5120	0	0
T20	0	286	0	0
T21	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	4059829	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	4059829	0	0
T1	31355	592	0	0
T2	68242	68	0	0
T3	3930	0	0	0
T4	208314	10847	0	0
T5	6296	220	0	0
T6	1929	0	0	0
T7	0	8	0	0
T8	0	7758	0	0
T12	1332	0	0	0
T17	121377	7168	0	0
T18	1364	0	0	0
T19	161606	15929	0	0
T20	0	286	0	0
T21	0	203	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	30753623	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	30753623	0	0
T1	31355	3027	0	0
T2	68242	7336	0	0
T3	3930	158	0	0
T4	208314	15168	0	0
T5	6296	1754	0	0
T6	1929	333	0	0
T12	1332	261	0	0
T17	121377	8030	0	0
T18	1364	136	0	0
T19	161606	7453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	395868381	34923344	0	0
DepthKnown_A	395868381	394939903	0	0
RvalidKnown_A	395868381	394939903	0	0
WreadyKnown_A	395868381	394939903	0	0
gen_passthru_fifo.paramCheckPass	1278	1278	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	34923344	0	0
T1	31355	3027	0	0
T2	68242	22793	0	0
T3	3930	158	0	0
T4	208314	68050	0	0
T5	6296	1754	0	0
T6	1929	333	0	0
T12	1332	261	0	0
T17	121377	8030	0	0
T18	1364	136	0	0
T19	161606	22975	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	395868381	394939903	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1278	1278	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T6,T18
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	2737348	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	2737348	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	2737348	0	0
T4	208314	5353	0	0
T5	6296	208	0	0
T6	1929	16	0	0
T7	546	0	0	0
T8	0	8267	0	0
T12	1332	0	0	0
T17	121377	2048	0	0
T18	1364	4	0	0
T19	161606	14272	0	0
T20	4957	0	0	0
T21	0	317	0	0
T22	489282	18128	0	0
T33	0	8162	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	2737348	0	0
T4	208314	5353	0	0
T5	6296	208	0	0
T6	1929	16	0	0
T7	546	0	0	0
T8	0	8267	0	0
T12	1332	0	0	0
T17	121377	2048	0	0
T18	1364	4	0	0
T19	161606	14272	0	0
T20	4957	0	0	0
T21	0	317	0	0
T22	489282	18128	0	0
T33	0	8162	0	0