Unified Coverage Report :: Module Instance :: tb.dut.u_tl_adapter_eflash.u_rspfifo

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.79	100.00	79.17			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.16	100.00	88.64			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.41	100.00	85.34			96.30	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.65	100.00	92.86		93.75	100.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.83	100.00	83.33			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.45	100.00	87.23	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.91	100.00	91.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.91	100.00	91.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.91	100.00	91.65			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.60	100.00	82.98	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.89	97.67	84.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	97.83	100.00	91.30	100.00		100.00

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Covered	Percent
Conditions	24	19	79.17
Logical	24	19	79.17
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T21,T49
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T20

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T54,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T21,T54
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	5343755	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	5343755	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	5343755	0	0
T1	31355	1717	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	13	0	0
T6	1929	0	0	0
T7	0	32	0	0
T8	0	41576	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	7	0	0
T21	0	165	0	0
T23	0	5	0	0
T33	0	41079	0	0
T58	0	16389	0	0
T59	0	131072	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	5343755	0	0
T1	31355	1717	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	13	0	0
T6	1929	0	0	0
T7	0	32	0	0
T8	0	41576	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	7	0	0
T21	0	165	0	0
T23	0	5	0	0
T33	0	41079	0	0
T58	0	16389	0	0
T59	0	131072	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T5,T20
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	34960710	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	34960710	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	34960710	0	0
T1	31355	502	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	52	0	0
T6	1929	0	0	0
T7	0	57	0	0
T8	0	132470	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	18	0	0
T21	0	60	0	0
T23	0	12	0	0
T33	0	154550	0	0
T58	0	28028	0	0
T59	0	196608	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	34960710	0	0
T1	31355	502	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	52	0	0
T6	1929	0	0	0
T7	0	57	0	0
T8	0	132470	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	18	0	0
T21	0	60	0	0
T23	0	12	0	0
T33	0	154550	0	0
T58	0	28028	0	0
T59	0	196608	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T5,T18
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	102695980	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	102695980	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	102695980	0	0
T1	31355	283	0	0
T2	68242	291	0	0
T3	3930	209	0	0
T4	208314	28432	0	0
T5	6296	1542	0	0
T6	1929	32	0	0
T12	1332	290	0	0
T17	121377	546	0	0
T18	1364	119	0	0
T19	161606	14626	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	102695980	0	0
T1	31355	283	0	0
T2	68242	291	0	0
T3	3930	209	0	0
T4	208314	28432	0	0
T5	6296	1542	0	0
T6	1929	32	0	0
T12	1332	290	0	0
T17	121377	546	0	0
T18	1364	119	0	0
T19	161606	14626	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T22
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T6,T22
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T6
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	97813044	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	97813044	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	97813044	0	0
T1	31355	246	0	0
T2	68242	65548	0	0
T3	3930	0	0	0
T4	208314	30664	0	0
T5	6296	0	0	0
T6	1929	432	0	0
T7	0	22	0	0
T8	0	113978	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	440	0	0
T22	0	187135	0	0
T33	0	146799	0	0
T58	0	9391	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	97813044	0	0
T1	31355	246	0	0
T2	68242	65548	0	0
T3	3930	0	0	0
T4	208314	30664	0	0
T5	6296	0	0	0
T6	1929	432	0	0
T7	0	22	0	0
T8	0	113978	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T21	0	440	0	0
T22	0	187135	0	0
T33	0	146799	0	0
T58	0	9391	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	20	83.33
Logical	24	20	83.33
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T33,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T5,T20

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T62,T66
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T33,T31
1	1	0	Not Covered
1	1	1	Covered	T1,T5,T20

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T20

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T62,T66
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T5,T20

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T33,T31
1	0	Covered	T1,T5,T20
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T5,T20
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T20
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T5,T20

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T20
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392755359	2791266	0	0
DepthKnown_A	392755359	391917953	0	0
RvalidKnown_A	392755359	391917953	0	0
WreadyKnown_A	392755359	391917953	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392755359	2791266	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	2791266	0	0
T1	31355	163	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	13	0	0
T6	1929	0	0	0
T7	0	11	0	0
T8	0	30832	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	7	0	0
T21	0	40	0	0
T31	0	8487	0	0
T33	0	32185	0	0
T58	0	8444	0	0
T63	0	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	2791266	0	0
T1	31355	163	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	13	0	0
T6	1929	0	0	0
T7	0	11	0	0
T8	0	30832	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T20	0	7	0	0
T21	0	40	0	0
T31	0	8487	0	0
T33	0	32185	0	0
T58	0	8444	0	0
T63	0	13	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T33
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392755359	53519836	0	0
DepthKnown_A	392755359	391917953	0	0
RvalidKnown_A	392755359	391917953	0	0
WreadyKnown_A	392755359	391917953	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392755359	53519836	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	53519836	0	0
T1	31355	847	0	0
T2	68242	130	0	0
T3	3930	794	0	0
T4	208314	1844	0	0
T5	6296	873	0	0
T6	1929	128	0	0
T12	1332	128	0	0
T17	121377	1344	0	0
T18	1364	256	0	0
T19	161606	1600	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	53519836	0	0
T1	31355	847	0	0
T2	68242	130	0	0
T3	3930	794	0	0
T4	208314	1844	0	0
T5	6296	873	0	0
T6	1929	128	0	0
T12	1332	128	0	0
T17	121377	1344	0	0
T18	1364	256	0	0
T19	161606	1600	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392755359	13957949	0	0
DepthKnown_A	392755359	391917953	0	0
RvalidKnown_A	392755359	391917953	0	0
WreadyKnown_A	392755359	391917953	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392755359	13957949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	13957949	0	0
T1	31355	315	0	0
T2	68242	65	0	0
T3	3930	396	0	0
T4	208314	636	0	0
T5	6296	384	0	0
T6	1929	64	0	0
T12	1332	64	0	0
T17	121377	544	0	0
T18	1364	128	0	0
T19	161606	544	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	13957949	0	0
T1	31355	315	0	0
T2	68242	65	0	0
T3	3930	396	0	0
T4	208314	636	0	0
T5	6296	384	0	0
T6	1929	64	0	0
T12	1332	64	0	0
T17	121377	544	0	0
T18	1364	128	0	0
T19	161606	544	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T60,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392920580	13150761	0	0
DepthKnown_A	392920580	392083174	0	0
RvalidKnown_A	392920580	392083174	0	0
WreadyKnown_A	392920580	392083174	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392920580	13150761	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	13150761	0	0
T1	31355	64	0	0
T2	68242	64	0	0
T3	3930	396	0	0
T4	208314	64	0	0
T5	6296	384	0	0
T6	1929	64	0	0
T12	1332	64	0	0
T17	121377	512	0	0
T18	1364	128	0	0
T19	161606	0	0	0
T20	0	242	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	392083174	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392920580	13150761	0	0
T1	31355	64	0	0
T2	68242	64	0	0
T3	3930	396	0	0
T4	208314	64	0	0
T5	6296	384	0	0
T6	1929	64	0	0
T12	1332	64	0	0
T17	121377	512	0	0
T18	1364	128	0	0
T19	161606	0	0	0
T20	0	242	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T8,T33,T58
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T8,T33,T58
1	1	0	Not Covered
1	1	1	Covered	T1,T7,T8

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T7,T8

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T8

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T8,T33,T58
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	392755359	3447090	0	0
DepthKnown_A	392755359	391917953	0	0
RvalidKnown_A	392755359	391917953	0	0
WreadyKnown_A	392755359	391917953	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	392755359	3447090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	3447090	0	0
T1	31355	163	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	0	0	0
T6	1929	0	0	0
T7	0	21	0	0
T8	0	39164	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T23	0	5	0	0
T24	0	8	0	0
T31	0	9612	0	0
T33	0	28978	0	0
T48	0	5	0	0
T58	0	7946	0	0
T59	0	131072	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	391917953	0	0
T1	31355	31256	0	0
T2	68242	68150	0	0
T3	3930	3301	0	0
T4	208314	208216	0	0
T5	6296	6156	0	0
T6	1929	1878	0	0
T12	1332	1239	0	0
T17	121377	121304	0	0
T18	1364	1211	0	0
T19	161606	161545	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	392755359	3447090	0	0
T1	31355	163	0	0
T2	68242	0	0	0
T3	3930	0	0	0
T4	208314	0	0	0
T5	6296	0	0	0
T6	1929	0	0	0
T7	0	21	0	0
T8	0	39164	0	0
T12	1332	0	0	0
T17	121377	0	0	0
T18	1364	0	0	0
T19	161606	0	0	0
T23	0	5	0	0
T24	0	8	0	0
T31	0	9612	0	0
T33	0	28978	0	0
T48	0	5	0	0
T58	0	7946	0	0
T59	0	131072	0	0