Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24125084	1		T1	117		T2	111743		T3	100
full_word	7909386	1		T1	44		T2	24501		T3	47

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32034170	1		T1	161		T2	136244		T3	147
auto[TlIntgErrCmd]	107	1		T180	2		T212	6		T226	5
auto[TlIntgErrData]	105	1		T180	4		T212	9		T226	4
auto[TlIntgErrBoth]	88	1		T180	4		T212	5		T226	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	27529436	1		T1	115		T2	123043		T3	94
auto[1]	4505034	1		T1	46		T2	13201		T3	53

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	23442687	1		T1	114		T2	109438		T3	94
auto[TlIntgErrNone]	partial	auto[1]	682126	1		T1	3		T2	2305		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	4086608	1		T1	1		T2	13605		T4	78
auto[TlIntgErrNone]	full_word	auto[1]	3822749	1		T1	43		T2	10896		T3	47
auto[TlIntgErrCmd]	partial	auto[0]	44	1		T180	2		T212	3		T226	2
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T212	3		T226	2		T231	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1		T226	1		T232	1		T352	1
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T231	1		T232	1		T357	1
auto[TlIntgErrData]	partial	auto[0]	49	1		T180	2		T212	1		T226	3
auto[TlIntgErrData]	partial	auto[1]	48	1		T180	2		T212	8		T226	1
auto[TlIntgErrData]	full_word	auto[0]	4	1		T231	1		T268	1		T356	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T352	1		T357	2		T354	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T180	1		T212	4		T226	1
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T180	2		T212	1		T232	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T180	1		T357	1		T358	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T268	1		T299	1		T356	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	24431	1		T63	857		T180	9		T182	1134
full_word	4469857	1		T2	37820		T4	143		T15	2

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4494009	1		T2	37820		T4	143		T15	2
auto[TlIntgErrCmd]	87	1		T180	4		T212	6		T226	3
auto[TlIntgErrData]	98	1		T180	3		T212	10		T226	3
auto[TlIntgErrBoth]	94	1		T180	3		T212	4		T226	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4463551	1		T2	37820		T4	143		T15	2
auto[1]	30737	1		T63	1179		T180	5		T182	1367

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1629	1		T63	63		T182	63		T181	18
auto[TlIntgErrNone]	partial	auto[1]	22556	1		T63	794		T182	1071		T181	157
auto[TlIntgErrNone]	full_word	auto[0]	4461803	1		T2	37820		T4	143		T15	2
auto[TlIntgErrNone]	full_word	auto[1]	8021	1		T63	385		T182	296		T181	62
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T180	1		T212	2		T226	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T180	3		T212	2		T226	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T212	1		T353	1		T359	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T212	1		T351	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1		T180	2		T212	4		T231	1
auto[TlIntgErrData]	partial	auto[1]	37	1		T180	1		T212	3		T226	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T212	2		T353	1		T360	1
auto[TlIntgErrData]	full_word	auto[1]	12	1		T212	1		T226	1		T232	1
auto[TlIntgErrBoth]	partial	auto[0]	29	1		T180	1		T226	1		T232	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1		T180	1		T212	4		T226	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T180	1		T226	1		T352	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T356	1		T353	3		T359	1