Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1683652640	1680151948	0	0
CheckNGreaterZero_A	4232	4232	0	0
GntImpliesReady_A	1683652640	451557826	0	0
GntImpliesValid_A	1683652640	451557826	0	0
GrantKnown_A	1683652640	1680151948	0	0
IdxKnown_A	1683652640	1680151948	0	0
IndexIsCorrect_A	1683652640	451557826	0	0
NoReadyValidNoGrant_A	1683652640	181272892	0	0
Priority_A	1683652640	475815126	0	0
ReadyAndValidImplyGrant_A	1683652640	451557826	0	0
ReqAndReadyImplyGrant_A	1683652640	451557826	0	0
ReqImpliesValid_A	1683652640	475815126	0	0
ValidKnown_A	1683652640	1680151948	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	1680151948	0	0
T1	3850896	3850448	0	0
T2	1138440	1138192	0	0
T3	5792	5224	0	0
T4	19048	18688	0	0
T5	2392900	2392580	0	0
T10	4432	3552	0	0
T11	1605132	1605088	0	0
T15	17952	17236	0	0
T16	1964456	1963924	0	0
T17	9536	9240	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4232	4232	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T10	4	4	0	0
T11	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	451557826	0	0
T1	1925448	1410	0	0
T2	1138440	263280	0	0
T3	5792	262	0	0
T4	19048	2980	0	0
T5	2392900	1083238	0	0
T6	0	31210	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	451557826	0	0
T1	1925448	1410	0	0
T2	1138440	263280	0	0
T3	5792	262	0	0
T4	19048	2980	0	0
T5	2392900	1083238	0	0
T6	0	31210	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	1680151948	0	0
T1	3850896	3850448	0	0
T2	1138440	1138192	0	0
T3	5792	5224	0	0
T4	19048	18688	0	0
T5	2392900	2392580	0	0
T10	4432	3552	0	0
T11	1605132	1605088	0	0
T15	17952	17236	0	0
T16	1964456	1963924	0	0
T17	9536	9240	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	1680151948	0	0
T1	3850896	3850448	0	0
T2	1138440	1138192	0	0
T3	5792	5224	0	0
T4	19048	18688	0	0
T5	2392900	2392580	0	0
T10	4432	3552	0	0
T11	1605132	1605088	0	0
T15	17952	17236	0	0
T16	1964456	1963924	0	0
T17	9536	9240	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	451557826	0	0
T1	1925448	1410	0	0
T2	1138440	263280	0	0
T3	5792	262	0	0
T4	19048	2980	0	0
T5	2392900	1083238	0	0
T6	0	31210	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	181272892	0	0
T1	1925448	384	0	0
T2	1138440	353810	0	0
T3	5792	512	0	0
T4	19048	1180	0	0
T5	2392900	3126	0	0
T6	0	62360	0	0
T10	4432	536	0	0
T11	1605132	2109952	0	0
T15	17952	1172	0	0
T16	1964456	256	0	0
T17	9536	314	0	0
T31	0	1202	0	0
T39	0	48	0	0
T40	0	296	0	0
T55	0	186	0	0
T56	7906	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	475815126	0	0
T1	1925448	1410	0	0
T2	1138440	330484	0	0
T3	5792	262	0	0
T4	19048	3086	0	0
T5	2392900	1083238	0	0
T6	0	38356	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	451557826	0	0
T1	1925448	1410	0	0
T2	1138440	263280	0	0
T3	5792	262	0	0
T4	19048	2980	0	0
T5	2392900	1083238	0	0
T6	0	31210	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	451557826	0	0
T1	1925448	1410	0	0
T2	1138440	263280	0	0
T3	5792	262	0	0
T4	19048	2980	0	0
T5	2392900	1083238	0	0
T6	0	31210	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	475815126	0	0
T1	1925448	1410	0	0
T2	1138440	330484	0	0
T3	5792	262	0	0
T4	19048	3086	0	0
T5	2392900	1083238	0	0
T6	0	38356	0	0
T10	4432	134	0	0
T11	1605132	514652	0	0
T15	17952	2462	0	0
T16	1964456	1088	0	0
T17	9536	958	0	0
T40	0	397334	0	0
T53	0	8	0	0
T56	7906	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1683652640	1680151948	0	0
T1	3850896	3850448	0	0
T2	1138440	1138192	0	0
T3	5792	5224	0	0
T4	19048	18688	0	0
T5	2392900	2392580	0	0
T10	4432	3552	0	0
T11	1605132	1605088	0	0
T15	17952	17236	0	0
T16	1964456	1963924	0	0
T17	9536	9240	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420913160	420037987	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	420913160	113969248	0	0
GntImpliesValid_A	420913160	113969248	0	0
GrantKnown_A	420913160	420037987	0	0
IdxKnown_A	420913160	420037987	0	0
IndexIsCorrect_A	420913160	113969248	0	0
NoReadyValidNoGrant_A	420913160	46930827	0	0
Priority_A	420913160	120233114	0	0
ReadyAndValidImplyGrant_A	420913160	113969248	0	0
ReqAndReadyImplyGrant_A	420913160	113969248	0	0
ReqImpliesValid_A	420913160	120233114	0	0
ValidKnown_A	420913160	420037987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113969248	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113969248	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113969248	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	46930827	0	0
T1	962724	192	0	0
T2	284610	90605	0	0
T3	1448	256	0	0
T4	4762	505	0	0
T5	598225	997	0	0
T10	1108	268	0	0
T11	401283	530688	0	0
T15	4488	256	0	0
T16	491114	128	0	0
T17	2384	157	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	120233114	0	0
T1	962724	705	0	0
T2	284610	90882	0	0
T3	1448	64	0	0
T4	4762	897	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113969248	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113969248	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	120233114	0	0
T1	962724	705	0	0
T2	284610	90882	0	0
T3	1448	64	0	0
T4	4762	897	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T6
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T6

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T6
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T6

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420913160	420037987	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	420913160	113760624	0	0
GntImpliesValid_A	420913160	113760624	0	0
GrantKnown_A	420913160	420037987	0	0
IdxKnown_A	420913160	420037987	0	0
IndexIsCorrect_A	420913160	113760624	0	0
NoReadyValidNoGrant_A	420913160	46930827	0	0
Priority_A	420913160	120024490	0	0
ReadyAndValidImplyGrant_A	420913160	113760624	0	0
ReqAndReadyImplyGrant_A	420913160	113760624	0	0
ReqImpliesValid_A	420913160	120024490	0	0
ValidKnown_A	420913160	420037987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113760624	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113760624	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113760624	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	46930827	0	0
T1	962724	192	0	0
T2	284610	90605	0	0
T3	1448	256	0	0
T4	4762	505	0	0
T5	598225	997	0	0
T10	1108	268	0	0
T11	401283	530688	0	0
T15	4488	256	0	0
T16	491114	128	0	0
T17	2384	157	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	120024490	0	0
T1	962724	705	0	0
T2	284610	90882	0	0
T3	1448	64	0	0
T4	4762	897	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113760624	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	113760624	0	0
T1	962724	705	0	0
T2	284610	72033	0	0
T3	1448	64	0	0
T4	4762	844	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	120024490	0	0
T1	962724	705	0	0
T2	284610	90882	0	0
T3	1448	64	0	0
T4	4762	897	0	0
T5	598225	272106	0	0
T10	1108	67	0	0
T11	401283	129429	0	0
T15	4488	64	0	0
T16	491114	544	0	0
T17	2384	162	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T15,T6
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420913160	420037987	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	420913160	111913977	0	0
GntImpliesValid_A	420913160	111913977	0	0
GrantKnown_A	420913160	420037987	0	0
IdxKnown_A	420913160	420037987	0	0
IndexIsCorrect_A	420913160	111913977	0	0
NoReadyValidNoGrant_A	420913160	43705619	0	0
Priority_A	420913160	117778761	0	0
ReadyAndValidImplyGrant_A	420913160	111913977	0	0
ReqAndReadyImplyGrant_A	420913160	111913977	0	0
ReqImpliesValid_A	420913160	117778761	0	0
ValidKnown_A	420913160	420037987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	43705619	0	0
T2	284610	86300	0	0
T3	1448	0	0	0
T4	4762	85	0	0
T5	598225	566	0	0
T6	0	31180	0	0
T10	1108	0	0	0
T11	401283	524288	0	0
T15	4488	330	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	601	0	0
T39	0	24	0	0
T40	0	148	0	0
T55	0	93	0	0
T56	3953	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	117778761	0	0
T2	284610	74360	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	19178	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	117778761	0	0
T2	284610	74360	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	19178	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T4,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T6
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T15,T6
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	420913160	420037987	0	0
CheckNGreaterZero_A	1058	1058	0	0
GntImpliesReady_A	420913160	111913977	0	0
GntImpliesValid_A	420913160	111913977	0	0
GrantKnown_A	420913160	420037987	0	0
IdxKnown_A	420913160	420037987	0	0
IndexIsCorrect_A	420913160	111913977	0	0
NoReadyValidNoGrant_A	420913160	43705619	0	0
Priority_A	420913160	117778761	0	0
ReadyAndValidImplyGrant_A	420913160	111913977	0	0
ReqAndReadyImplyGrant_A	420913160	111913977	0	0
ReqImpliesValid_A	420913160	117778761	0	0
ValidKnown_A	420913160	420037987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	43705619	0	0
T2	284610	86300	0	0
T3	1448	0	0	0
T4	4762	85	0	0
T5	598225	566	0	0
T6	0	31180	0	0
T10	1108	0	0	0
T11	401283	524288	0	0
T15	4488	330	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	601	0	0
T39	0	24	0	0
T40	0	148	0	0
T55	0	93	0	0
T56	3953	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	117778761	0	0
T2	284610	74360	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	19178	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	111913977	0	0
T2	284610	59607	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	15605	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	117778761	0	0
T2	284610	74360	0	0
T3	1448	67	0	0
T4	4762	646	0	0
T5	598225	269513	0	0
T6	0	19178	0	0
T10	1108	0	0	0
T11	401283	127897	0	0
T15	4488	1167	0	0
T16	491114	0	0	0
T17	2384	317	0	0
T40	0	198667	0	0
T53	0	4	0	0
T56	3953	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0