Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.49	100.00	96.92	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.36	100.00	83.96		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T218,T9
1	0	Covered	T124,T218,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T124,T218,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T218,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T3,T4

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T3,T4

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T15
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T3,T4

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T1,T2,T3

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T1,T2,T3

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T2,T3
StCalcMask	237	Covered	T1,T2,T3
StCalcPlainEcc	215	Covered	T1,T2,T3
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T3
StPostPack	218	Covered	T2,T3,T4
StPrePack	195	Covered	T2,T3,T4
StReqFlash	237	Covered	T1,T2,T3
StScrambleData	244	Covered	T1,T2,T3
StWaitFlash	270	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T2,T3
StCalcMask->StScrambleData	244	Covered	T1,T2,T3
StCalcPlainEcc->StCalcMask	237	Covered	T1,T2,T3
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T17
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T2,T3
StIdle->StPrePack	195	Covered	T2,T3,T4
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T4
StPackData->StPostPack	218	Covered	T2,T3,T4
StPostPack->StCalcPlainEcc	231	Covered	T2,T3,T4
StPrePack->StPackData	205	Covered	T2,T4,T17
StReqFlash->StIdle	273	Covered	T1,T2,T4
StReqFlash->StWaitFlash	270	Covered	T1,T2,T3
StScrambleData->StCalcEcc	252	Covered	T1,T2,T3
StWaitFlash->StIdle	280	Covered	T1,T2,T3

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T3
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T17
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T3
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T3
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T3
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T3
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T3
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T4,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T4,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T3
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T13,T14

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	841826320	2401452	0	0
PostPackRule_A	841826320	29801	0	0
PrePackRule_A	841826320	15178	0	0
WidthCheck_A	2116	2116	0	0
u_state_regs_A	841826320	840075974	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841826320	2401452	0	0
T1	962724	4	0	0
T2	569220	782	0	0
T3	2896	1	0	0
T4	9524	2	0	0
T5	1196450	58	0	0
T6	0	216	0	0
T10	2216	0	0	0
T11	802566	65920	0	0
T15	8976	5	0	0
T16	982228	0	0	0
T17	4768	2	0	0
T18	0	14	0	0
T47	0	286	0	0
T54	0	321	0	0
T55	0	3	0	0
T56	3953	0	0	0
T105	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841826320	29801	0	0
T2	569220	277	0	0
T3	2896	1	0	0
T4	9524	2	0	0
T5	1196450	41	0	0
T6	0	65	0	0
T10	2216	0	0	0
T11	802566	0	0	0
T15	8976	2	0	0
T16	982228	0	0	0
T17	4768	2	0	0
T19	0	107	0	0
T20	0	1	0	0
T31	0	36	0	0
T37	0	1	0	0
T55	0	1	0	0
T56	7906	0	0	0
T219	0	12	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841826320	15178	0	0
T2	569220	114	0	0
T3	2896	0	0	0
T4	9524	1	0	0
T5	1196450	19	0	0
T6	0	59	0	0
T10	2216	0	0	0
T11	802566	0	0	0
T15	8976	0	0	0
T16	982228	0	0	0
T17	4768	1	0	0
T18	0	1	0	0
T19	0	32	0	0
T31	0	20	0	0
T37	0	3	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	7906	0	0	0
T81	0	173	0	0
T105	0	1	0	0
T106	0	6	0	0
T219	0	6	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2116	2116	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T10	2	2	0	0
T11	2	2	0	0
T15	2	2	0	0
T16	2	2	0	0
T17	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841826320	840075974	0	0
T1	1925448	1925224	0	0
T2	569220	569096	0	0
T3	2896	2612	0	0
T4	9524	9344	0	0
T5	1196450	1196290	0	0
T10	2216	1776	0	0
T11	802566	802544	0	0
T15	8976	8618	0	0
T16	982228	981962	0	0
T17	4768	4620	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T218,T9
1	0	Covered	T124,T218,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T124,T218,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T218,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T2,T4,T17

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T5

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T4,T5

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T1,T2,T4
1	1	Covered	T2,T4,T17

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T4,T17

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T2,T4,T17
1	Covered	T1,T2,T11

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T5,T6
1	Covered	T1,T2,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T5
1	Covered	T1,T2,T4

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T1,T2,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T11
1	1	Covered	T1,T2,T11

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T1,T2,T11
StCalcMask	237	Covered	T1,T2,T11
StCalcPlainEcc	215	Covered	T1,T2,T4
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T2,T4
StPostPack	218	Covered	T2,T4,T17
StPrePack	195	Covered	T2,T4,T5
StReqFlash	237	Covered	T1,T2,T4
StScrambleData	244	Covered	T1,T2,T11
StWaitFlash	270	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T1,T2,T11
StCalcMask->StScrambleData	244	Covered	T1,T2,T11
StCalcPlainEcc->StCalcMask	237	Covered	T1,T2,T11
StCalcPlainEcc->StReqFlash	237	Covered	T2,T4,T17
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T1,T2,T4
StIdle->StPrePack	195	Covered	T2,T4,T5
StPackData->StCalcPlainEcc	215	Covered	T1,T2,T4
StPackData->StPostPack	218	Covered	T2,T4,T17
StPostPack->StCalcPlainEcc	231	Covered	T2,T4,T17
StPrePack->StPackData	205	Covered	T2,T4,T5
StReqFlash->StIdle	273	Covered	T1,T2,T4
StReqFlash->StWaitFlash	270	Covered	T1,T2,T4
StScrambleData->StCalcEcc	252	Covered	T1,T2,T11
StWaitFlash->StIdle	280	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T4
0	0	1	Covered	T1,T2,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T5
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T17
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T4,T17
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T2,T11
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T4,T17
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T2,T11
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T2,T11
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T2,T11
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T2,T11
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T11
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T2,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T2,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T4,T5
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T13,T14

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	Covered	T1,T2,T11
0	0	0	1	-	Covered	T1,T2,T11
0	0	0	0	1	Covered	T1,T2,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	420913160	1207833	0	0
PostPackRule_A	420913160	17166	0	0
PrePackRule_A	420913160	8808	0	0
WidthCheck_A	1058	1058	0	0
u_state_regs_A	420913160	420037987	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	1207833	0	0
T1	962724	4	0	0
T2	284610	478	0	0
T3	1448	0	0	0
T4	4762	1	0	0
T5	598225	31	0	0
T6	0	159	0	0
T10	1108	0	0	0
T11	401283	33152	0	0
T15	4488	0	0	0
T16	491114	0	0	0
T17	2384	1	0	0
T18	0	14	0	0
T47	0	286	0	0
T54	0	321	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	17166	0	0
T2	284610	138	0	0
T3	1448	0	0	0
T4	4762	1	0	0
T5	598225	19	0	0
T6	0	44	0	0
T10	1108	0	0	0
T11	401283	0	0	0
T15	4488	0	0	0
T16	491114	0	0	0
T17	2384	1	0	0
T19	0	65	0	0
T20	0	1	0	0
T31	0	19	0	0
T37	0	1	0	0
T56	3953	0	0	0
T219	0	12	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	8808	0	0
T2	284610	74	0	0
T3	1448	0	0	0
T4	4762	1	0	0
T5	598225	8	0	0
T6	0	39	0	0
T10	1108	0	0	0
T11	401283	0	0	0
T15	4488	0	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T19	0	32	0	0
T31	0	11	0	0
T37	0	1	0	0
T56	3953	0	0	0
T81	0	173	0	0
T106	0	6	0	0
T219	0	6	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T220,T221
1	0	Covered	T9,T220,T221

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T9,T220,T221

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T220,T221
1	0	Covered	T2,T3,T4

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T2,T3,T4

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T17

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T3,T17

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T15
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T15

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T2,T4,T15

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T11
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T7,T8
1	Covered	T2,T3,T4

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T17,T5
1	Covered	T2,T3,T15

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T2,T3,T4

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T2,T4,T15

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T15
1	1	Covered	T2,T3,T4

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T11
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T11
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T3,T4
1	1	0	Covered	T2,T4,T15
1	1	1	Covered	T2,T3,T4

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T15

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T2,T3,T15
StCalcMask	237	Covered	T2,T3,T15
StCalcPlainEcc	215	Covered	T2,T3,T4
StDisabled	193	Covered	T10,T11,T12
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T2,T3,T4
StPostPack	218	Covered	T2,T3,T4
StPrePack	195	Covered	T2,T3,T17
StReqFlash	237	Covered	T2,T3,T4
StScrambleData	244	Covered	T2,T3,T15
StWaitFlash	270	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T2,T3,T15
StCalcMask->StScrambleData	244	Covered	T2,T3,T15
StCalcPlainEcc->StCalcMask	237	Covered	T2,T3,T15
StCalcPlainEcc->StReqFlash	237	Covered	T4,T17,T5
StIdle->StDisabled	193	Covered	T10,T11,T12
StIdle->StPackData	197	Covered	T2,T3,T4
StIdle->StPrePack	195	Covered	T2,T3,T17
StPackData->StCalcPlainEcc	215	Covered	T2,T4,T15
StPackData->StPostPack	218	Covered	T2,T3,T4
StPostPack->StCalcPlainEcc	231	Covered	T2,T3,T4
StPrePack->StPackData	205	Covered	T2,T17,T5
StReqFlash->StIdle	273	Covered	T2,T4,T15
StReqFlash->StWaitFlash	270	Covered	T2,T3,T4
StScrambleData->StCalcEcc	252	Covered	T2,T3,T15
StWaitFlash->StIdle	280	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T3,T4
0	1	Covered	T2,T4,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T17
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T15
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T2,T4,T15
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T2,T4,T15
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T7,T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T15
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T17,T5
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T15
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T15
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T15
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T15
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T2,T3,T4
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T2,T4,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T2,T4,T15
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T2,T4,T15
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T13,T14

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T4
0	0	1	-	-	Covered	T2,T3,T15
0	0	0	1	-	Covered	T2,T3,T15
0	0	0	0	1	Covered	T2,T3,T4
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	420913160	1193619	0	0
PostPackRule_A	420913160	12635	0	0
PrePackRule_A	420913160	6370	0	0
WidthCheck_A	1058	1058	0	0
u_state_regs_A	420913160	420037987	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	1193619	0	0
T2	284610	304	0	0
T3	1448	1	0	0
T4	4762	1	0	0
T5	598225	27	0	0
T6	0	57	0	0
T10	1108	0	0	0
T11	401283	32768	0	0
T15	4488	5	0	0
T16	491114	0	0	0
T17	2384	1	0	0
T55	0	3	0	0
T56	3953	0	0	0
T105	0	1	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	12635	0	0
T2	284610	139	0	0
T3	1448	1	0	0
T4	4762	1	0	0
T5	598225	22	0	0
T6	0	21	0	0
T10	1108	0	0	0
T11	401283	0	0	0
T15	4488	2	0	0
T16	491114	0	0	0
T17	2384	1	0	0
T19	0	42	0	0
T31	0	17	0	0
T55	0	1	0	0
T56	3953	0	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	6370	0	0
T2	284610	40	0	0
T3	1448	0	0	0
T4	4762	0	0	0
T5	598225	11	0	0
T6	0	20	0	0
T10	1108	0	0	0
T11	401283	0	0	0
T15	4488	0	0	0
T16	491114	0	0	0
T17	2384	1	0	0
T18	0	1	0	0
T31	0	9	0	0
T37	0	2	0	0
T53	0	1	0	0
T55	0	2	0	0
T56	3953	0	0	0
T105	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1058	1058	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0