Unified Coverage Report :: Module Instance :: tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.52	100.00	90.09			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.44	100.00	87.18	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.52	100.00	90.09			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	80.56			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.52	100.00	90.09			100.00	100.00	u_rd

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T55
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T4,T15
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420717781	50450110	0	0
DepthKnown_A	420717781	419842608	0	0
RvalidKnown_A	420717781	419842608	0	0
WreadyKnown_A	420717781	419842608	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	420717781	50450110	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	50450110	0	0
T2	284610	110951	0	0
T3	1448	0	0	0
T4	4762	85	0	0
T5	598225	566	0	0
T6	0	38966	0	0
T10	1108	0	0	0
T11	401283	524288	0	0
T15	4488	330	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	601	0	0
T39	0	26	0	0
T40	0	148	0	0
T55	0	160	0	0
T56	3953	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	50450110	0	0
T2	284610	110951	0	0
T3	1448	0	0	0
T4	4762	85	0	0
T5	598225	566	0	0
T6	0	38966	0	0
T10	1108	0	0	0
T11	401283	524288	0	0
T15	4488	330	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	601	0	0
T39	0	26	0	0
T40	0	148	0	0
T55	0	160	0	0
T56	3953	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T13,T14,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T4,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T15,T11
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T4,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T4,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420717781	13209264	0	0
DepthKnown_A	420717781	419842608	0	0
RvalidKnown_A	420717781	419842608	0	0
WreadyKnown_A	420717781	419842608	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	420717781	13209264	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	13209264	0	0
T2	284610	50873	0	0
T3	1448	0	0	0
T4	4762	30	0	0
T5	598225	197	0	0
T6	0	19607	0	0
T10	1108	0	0	0
T11	401283	262144	0	0
T15	4488	130	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	211	0	0
T39	0	13	0	0
T40	0	55	0	0
T55	0	55	0	0
T56	3953	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	419842608	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	420717781	13209264	0	0
T2	284610	50873	0	0
T3	1448	0	0	0
T4	4762	30	0	0
T5	598225	197	0	0
T6	0	19607	0	0
T10	1108	0	0	0
T11	401283	262144	0	0
T15	4488	130	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T31	0	211	0	0
T39	0	13	0	0
T40	0	55	0	0
T55	0	55	0	0
T56	3953	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T15,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T40
1	0	1	Covered	T2,T15,T11
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T11

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T15,T11
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T15,T11

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	420913160	11865289	0	0
DepthKnown_A	420913160	420037987	0	0
RvalidKnown_A	420913160	420037987	0	0
WreadyKnown_A	420913160	420037987	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	420913160	11865289	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	11865289	0	0
T2	284610	73982	0	0
T3	1448	0	0	0
T4	4762	0	0	0
T5	598225	0	0	0
T6	0	25394	0	0
T10	1108	0	0	0
T11	401283	262144	0	0
T15	4488	130	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T19	0	29396	0	0
T21	0	110	0	0
T39	0	10	0	0
T40	0	12	0	0
T56	3953	0	0	0
T59	0	16	0	0
T62	0	202	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	420037987	0	0
T1	962724	962612	0	0
T2	284610	284548	0	0
T3	1448	1306	0	0
T4	4762	4672	0	0
T5	598225	598145	0	0
T10	1108	888	0	0
T11	401283	401272	0	0
T15	4488	4309	0	0
T16	491114	490981	0	0
T17	2384	2310	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	420913160	11865289	0	0
T2	284610	73982	0	0
T3	1448	0	0	0
T4	4762	0	0	0
T5	598225	0	0	0
T6	0	25394	0	0
T10	1108	0	0	0
T11	401283	262144	0	0
T15	4488	130	0	0
T16	491114	0	0	0
T17	2384	0	0	0
T19	0	29396	0	0
T21	0	110	0	0
T39	0	10	0	0
T40	0	12	0	0
T56	3953	0	0	0
T59	0	16	0	0
T62	0	202	0	0