Unified Coverage Report :: Module :: tlul_adapter_sram

Module : tlul_adapter_sram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.34	100.00	77.05			96.30	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo	84.25	100.00	66.67			84.62	85.71
tb.dut.u_to_rd_fifo	93.86	100.00	79.13			96.30	100.00
tb.dut.u_tl_adapter_eflash	95.41	100.00	85.34			96.30	100.00

---

Module Instance : tb.dut.u_to_prog_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.25	100.00	66.67			84.62	85.71

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.71	89.33	66.13			82.14	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.34	97.12	92.80	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	87.32	100.00	74.29			75.00	100.00
u_reqfifo	92.36	100.00	75.00			94.44	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	69.33	91.43	57.14			68.75	60.00
u_sram_byte	100.00	100.00
u_sramreqfifo	72.63	94.44	54.84			81.25	60.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_to_rd_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.86	100.00	79.13			96.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.22	88.89	78.07	100.00		89.16	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.34	97.12	92.80	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_err	66.91	76.92	65.71			25.00	100.00
u_reqfifo	92.36	100.00	75.00			94.44	100.00
u_rsp_gen	91.67	83.33					100.00
u_rspfifo	98.30	100.00	91.49	100.00		100.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	91.67	100.00	72.22			94.44	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

---

Module Instance : tb.dut.u_tl_adapter_eflash

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.41	100.00	85.34			96.30	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.45	92.71	85.02	100.00		94.51	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.34	97.12	92.80	98.44		100.00	98.33	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_cmd_intg_check.u_cmd_intg_chk	100.00	100.00		100.00			100.00
u_err	81.79	100.00	77.14			50.00	100.00
u_reqfifo	96.53	100.00	86.11			100.00	100.00
u_rsp_gen	100.00	100.00					100.00
u_rspfifo	97.16	100.00	88.64			100.00	100.00
u_sram_byte	100.00	100.00
u_sramreqfifo	96.53	100.00	86.11			100.00	100.00
u_tlul_data_integ_enc_data	0.00	0.00
u_tlul_data_integ_enc_instr	0.00	0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
84.25	100.00

tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
ALWAYS	94	3	3	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	0	0
CONT_ASSIGN	410	0	0
CONT_ASSIGN	417	0	0
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97		unreachable
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
126	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408		unreachable
410		unreachable
417		unreachable
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
93.86	100.00

tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408	1	1
410	1	1
417	1	1
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :

SCORE	LINE
95.41	100.00

tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408	1	1
410	1	1
417	1	1
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
84.25	66.67

tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	111	74	66.67
Logical	111	74	66.67
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T4,T15
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15
1	1	Covered	T1,T4,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T20
1	1	Covered	T1,T4,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T27
1	1	Covered	T1,T4,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T15
1	1	Not Covered

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T20,T27
1	0	1	Covered	T1,T4,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T4,T15

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15
1	1	Not Covered

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T15
1	0	Unreachable
1	1	Unreachable

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
93.86	79.13

tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	115	91	79.13
Logical	115	91	79.13
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T36
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T13,T14,T36
0	1	0	Covered	T13,T14,T36
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T20
1	1	Covered	T1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T56,T57,T13

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T57,T13
1	1	Covered	T1,T2,T3

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T56,T57,T13

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T20,T27,T44
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T27,T44
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :

SCORE	COND
95.41	85.34

tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	116	99	85.34
Logical	116	99	85.34
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T57,T58

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T56,T57,T58
0	1	0	Unreachable
1	0	0	Covered	T56,T57,T58

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T16

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T3,T16

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T3,T15
0	0	0	0	0	1	Covered	T58
0	0	0	0	1	0	Covered	T1,T3,T16
0	0	0	1	0	0	Covered	T39,T59,T60
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T21
1	1	Covered	T1,T3,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T3,T15

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T57
1	Covered	T1,T3,T15

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T39,T56,T59
1	0	Covered	T33,T61,T62

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T39,T56,T59
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T15

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T61,T62
1	1	Covered	T1,T3,T15

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T39,T56,T59
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T57

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T57

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T15
1	1	Covered	T39,T33,T61

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T37,T45,T46
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T39,T56,T59
1	1	1	Covered	T1,T3,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T56,T59
1	1	Covered	T1,T3,T15

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

---

Branch Coverage for Module : tlul_adapter_sram

	Line No.	Total	Covered	Percent
Branches		27	26	96.30
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	326	2	2	100.00
TERNARY	449	2	2	100.00
IF	94	3	3	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	359	2	2	100.00
IF	371	2	2	100.00
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	449	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T56,T6,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T39,T56,T59
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T1,T4,T15
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_adapter_sram

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	1306798905	1304187372	0	0
DataIntgOptions_A	3186	3186	0	0
ReqOutKnown_A	1306798905	1304187372	0	0
SramDwHasByteGranularity_A	3186	3186	0	0
SramDwIsMultipleOfTlulWidth_A	3186	3186	0	0
TlOutKnown_A	1306798905	1304187372	0	0
TlOutPayloadKnown_A	1306798905	14305225	0	0
TlOutPayloadKnown_AKnownEnable	1306798905	1304187372	0	0
WdataOutKnown_A	1306798905	1304187372	0	0
WeOutKnown_A	1306798905	1304187372	0	0
WmaskOutKnown_A	1306798905	1304187372	0	0
adapterNoReadOrWrite	3186	3186	0	0
rvalidHighReqFifoEmpty	1306798905	7884093	0	0
rvalidHighWhenRspFifoFull	1306216973	7877496	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3186	3186	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3186	3186	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3186	3186	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	14305225	0	0
T1	109008	2216	0	0
T2	4482	12	0	0
T3	2504286	29557	0	0
T4	321762	9216	0	0
T5	13710	169	0	0
T15	14340	552	0	0
T16	477132	4408	0	0
T17	9717	0	0	0
T18	5694	32	0	0
T19	1490976	18784	0	0
T20	0	26973	0	0
T21	0	16135	0	0
T22	0	178	0	0
T23	0	96	0	0
T24	0	22	0	0
T31	0	16400	0	0
T39	0	546	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	1304187372	0	0
T1	109008	108771	0	0
T2	4482	4293	0	0
T3	2504286	2503767	0	0
T4	321762	321612	0	0
T5	13710	13533	0	0
T15	14340	13917	0	0
T16	477132	448422	0	0
T17	9717	9498	0	0
T18	5694	5280	0	0
T19	1490976	1490949	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	3186	3186	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T15	3	3	0	0
T16	3	3	0	0
T17	3	3	0	0
T18	3	3	0	0
T19	3	3	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306798905	7884093	0	0
T1	72672	1265	0	0
T2	2988	12	0	0
T3	1669524	29557	0	0
T4	214508	4096	0	0
T5	9140	127	0	0
T15	9560	309	0	0
T16	318088	2896	0	0
T17	6478	0	0	0
T18	3796	0	0	0
T19	993984	0	0	0
T20	0	4096	0	0
T21	0	16135	0	0
T22	0	178	0	0
T23	0	80	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306216973	7877496	0	0
T1	72672	1265	0	0
T2	2988	12	0	0
T3	1669524	29557	0	0
T4	214508	4096	0	0
T5	9140	127	0	0
T15	9560	309	0	0
T16	318088	2896	0	0
T17	6478	0	0	0
T18	3796	0	0	0
T19	993984	0	0	0
T20	0	4096	0	0
T21	0	16135	0	0
T22	0	178	0	0
T23	0	80	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0

Line Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
TOTAL		61	61	100.00
ALWAYS	94	3	3	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	0	0
CONT_ASSIGN	410	0	0
CONT_ASSIGN	417	0	0
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97		unreachable
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
126	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408		unreachable
410		unreachable
417		unreachable
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Covered	Percent
Conditions	111	74	66.67
Logical	111	74	66.67
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Unreachable
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T4,T15
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Unreachable
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15
1	1	Covered	T1,T4,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T20
1	1	Covered	T1,T4,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T20,T27
1	1	Covered	T1,T4,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T15
1	Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T4,T15
1	1	Not Covered

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T20,T27
1	0	1	Covered	T1,T4,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T5,T18
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T15
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T4,T15

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T1,T4,T15

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T15
1	1	Not Covered

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T15
1	0	Unreachable
1	1	Unreachable

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo

	Line No.	Total	Covered	Percent
Branches		26	22	84.62
TERNARY	108	2	2	100.00
TERNARY	293	2	1	50.00
TERNARY	299	3	1	33.33
TERNARY	326	2	2	100.00
TERNARY	449	2	1	50.00
IF	94	2	2	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	359	2	2	100.00
IF	371	2	2	100.00
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	449	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Unreachable
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6
1	0	1	Covered	T6
1	0	0	Covered	T1,T4,T15
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T6
1	0	Covered	T1,T4,T15
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_prog_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	12	85.71
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	12	85.71

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	435599635	434729124	0	0
DataIntgOptions_A	1062	1062	0	0
ReqOutKnown_A	435599635	434729124	0	0
SramDwHasByteGranularity_A	1062	1062	0	0
SramDwIsMultipleOfTlulWidth_A	1062	1062	0	0
TlOutKnown_A	435599635	434729124	0	0
TlOutPayloadKnown_A	435599635	3581913	0	0
TlOutPayloadKnown_AKnownEnable	435599635	434729124	0	0
WdataOutKnown_A	435599635	434729124	0	0
WeOutKnown_A	435599635	434729124	0	0
WmaskOutKnown_A	435599635	434729124	0	0
adapterNoReadOrWrite	1062	1062	0	0
rvalidHighReqFifoEmpty	435599635	0	0	0
rvalidHighWhenRspFifoFull	435599635	0	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	3581913	0	0
T1	36336	951	0	0
T2	1494	0	0	0
T3	834762	0	0	0
T4	107254	5120	0	0
T5	4570	42	0	0
T15	4780	243	0	0
T16	159044	1512	0	0
T17	3239	0	0	0
T18	1898	32	0	0
T19	496992	18784	0	0
T20	0	14068	0	0
T23	0	16	0	0
T24	0	16	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	0	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	0	0	0

Line Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408	1	1
410	1	1
417	1	1
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Covered	Percent
Conditions	115	91	79.13
Logical	115	91	79.13
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T36
1	0	Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T13,T14,T36
0	1	0	Covered	T13,T14,T36
1	0	0	Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T15,T17
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	1	Unreachable
0	0	0	0	1	0	Covered	T1,T2,T3
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T15,T20
1	1	Covered	T1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T2,T3

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T2,T3

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T56,T57,T13

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T57,T13
1	1	Covered	T1,T2,T3

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T56,T57,T13

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T5
1	0	1	Covered	T20,T27,T44
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T27,T44
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo

	Line No.	Total	Covered	Percent
Branches		27	26	96.30
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	326	2	2	100.00
TERNARY	449	2	2	100.00
IF	94	3	3	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	359	2	2	100.00
IF	371	2	2	100.00
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	449	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T13,T14
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T6
1	0	1	Covered	T1,T2,T3
1	0	0	Covered	T6
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T2,T3
1	0	Covered	T6
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_to_rd_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	435599635	434729124	0	0
DataIntgOptions_A	1062	1062	0	0
ReqOutKnown_A	435599635	434729124	0	0
SramDwHasByteGranularity_A	1062	1062	0	0
SramDwIsMultipleOfTlulWidth_A	1062	1062	0	0
TlOutKnown_A	435599635	434729124	0	0
TlOutPayloadKnown_A	435599635	4884335	0	0
TlOutPayloadKnown_AKnownEnable	435599635	434729124	0	0
WdataOutKnown_A	435599635	434729124	0	0
WeOutKnown_A	435599635	434729124	0	0
WmaskOutKnown_A	435599635	434729124	0	0
adapterNoReadOrWrite	1062	1062	0	0
rvalidHighReqFifoEmpty	435599635	3298015	0	0
rvalidHighWhenRspFifoFull	435017703	3291418	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	4884335	0	0
T1	36336	1141	0	0
T2	1494	12	0	0
T3	834762	13440	0	0
T4	107254	4096	0	0
T5	4570	12	0	0
T15	4780	305	0	0
T16	159044	2896	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T20	0	12905	0	0
T22	0	160	0	0
T23	0	74	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	3298015	0	0
T1	36336	1141	0	0
T2	1494	12	0	0
T3	834762	13440	0	0
T4	107254	4096	0	0
T5	4570	12	0	0
T15	4780	305	0	0
T16	159044	2896	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T20	0	4096	0	0
T22	0	160	0	0
T23	0	74	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	435017703	3291418	0	0
T1	36336	1141	0	0
T2	1494	12	0	0
T3	834762	13440	0	0
T4	107254	4096	0	0
T5	4570	12	0	0
T15	4780	305	0	0
T16	159044	2896	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T20	0	4096	0	0
T22	0	160	0	0
T23	0	74	0	0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
TOTAL		65	65	100.00
ALWAYS	94	4	4	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	115	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
CONT_ASSIGN	140	1	1	100.00
CONT_ASSIGN	152	1	1	100.00
CONT_ASSIGN	224	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	226	1	1	100.00
ALWAYS	231	8	8	100.00
ALWAYS	251	6	6	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	269	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
ALWAYS	356	6	6	100.00
ALWAYS	368	5	5	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	392	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	417	1	1	100.00
ALWAYS	423	3	3	100.00
CONT_ASSIGN	444	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	454	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
94	1	1
95	1	1
96	1	1
97	1	1
			MISSING_ELSE
103	1	1
108	1	1
115	1	1
120	1	1
140	1	1
152	1	1
224	1	1
225	1	1
226	1	1
231	1	1
233	1	1
234	1	1
236	1	1
237	1	1
238	1	1
241	1	1
244	1	1
251	1	1
253	1	1
254	1	1
255	1	1
257	1	1
260	1	1
265	1	1
269	1	1
288	1	1
293	1	1
299	1	1
303	1	1
323	1	1
324	1	1
325	1	1
326	1	1
356	1	1
357	1	1
359	1	1
360	1	1
361	1	1
362	1	1
			MISSING_ELSE
368	1	1
369	1	1
371	1	1
372	1	1
373	1	1
			MISSING_ELSE
379	1	1
380	1	1
389	1	1
390	1	1
392	1	1
393	1	1
400	1	1
403	1	1
407	1	1
408	1	1
410	1	1
417	1	1
423	1	1
427	1	1
429	1	1
			MISSING_ELSE
444	1	1
449	1	1
454		unreachable

---

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Covered	Percent
Conditions	116	99	85.34
Logical	116	99	85.34
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T57,T58

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T56,T57,T58
0	1	0	Unreachable
1	0	0	Covered	T56,T57,T58

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T16

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T16
1	0	Covered	T1,T3,T16

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T16
1	Covered	T1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Covered	T1,T3,T15
0	0	0	0	0	1	Covered	T58
0	0	0	0	1	0	Covered	T1,T3,T16
0	0	0	1	0	0	Covered	T39,T59,T60
0	0	1	0	0	0	Unreachable
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T21
1	1	Covered	T1,T3,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6
1	Covered	T1,T3,T15

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------

-1-	Status	Tests
0	Covered	T6,T57
1	Covered	T1,T3,T15

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T15
0	1	Covered	T39,T56,T59
1	0	Covered	T33,T61,T62

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Covered	T39,T56,T59
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T3,T15

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T33,T61,T62
1	1	Covered	T1,T3,T15

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T39,T56,T59
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T57

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T57

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T15
1	1	Covered	T39,T33,T61

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T5
1	0	1	Covered	T37,T45,T46
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T5
1	1	0	Covered	T39,T56,T59
1	1	1	Covered	T1,T3,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T3,T15
1	1	Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T15
1	0	Not Covered
1	1	Covered	T1,T3,T15

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T39,T56,T59
1	1	Covered	T1,T3,T15

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T15

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Line No.	Total	Covered	Percent
Branches		27	26	96.30
TERNARY	108	2	2	100.00
TERNARY	293	2	2	100.00
TERNARY	299	3	2	66.67
TERNARY	326	2	2	100.00
TERNARY	449	2	2	100.00
IF	94	3	3	100.00
IF	233	4	4	100.00
IF	253	3	3	100.00
IF	359	2	2	100.00
IF	371	2	2	100.00
IF	427	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	108	(((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	293	((vld_rd_rsp & (~d_error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	299	((vld_rd_rsp && reqfifo_rdata.error)) ? 
-2-:	299	(vld_rd_rsp) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Covered	T1,T3,T15
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	326	(tl_i_int.a_valid) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	449	(((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	94	if ((!rst_ni))
-2-:	96	if ((intg_error || rsp_fifo_error))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T56,T6,T57
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	233	if (reqfifo_rvalid)
-2-:	234	if (reqfifo_rdata.error)
-3-:	237	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T39,T56,T59
1	0	1	Covered	T1,T3,T15
1	0	0	Covered	T6
0	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	253	if (reqfifo_rvalid)
-2-:	254	if ((reqfifo_rdata.op == OpRead))

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T1,T3,T15
1	0	Covered	T6,T57
0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	359	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	371	if (tl_i_int.a_valid)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	427	if ((|sramreqfifo_rdata.mask))

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AddrOutKnown_A	435599635	434729124	0	0
DataIntgOptions_A	1062	1062	0	0
ReqOutKnown_A	435599635	434729124	0	0
SramDwHasByteGranularity_A	1062	1062	0	0
SramDwIsMultipleOfTlulWidth_A	1062	1062	0	0
TlOutKnown_A	435599635	434729124	0	0
TlOutPayloadKnown_A	435599635	5838977	0	0
TlOutPayloadKnown_AKnownEnable	435599635	434729124	0	0
WdataOutKnown_A	435599635	434729124	0	0
WeOutKnown_A	435599635	434729124	0	0
WmaskOutKnown_A	435599635	434729124	0	0
adapterNoReadOrWrite	1062	1062	0	0
rvalidHighReqFifoEmpty	435599635	4586078	0	0
rvalidHighWhenRspFifoFull	435599635	4586078	0	0

AddrOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

DataIntgOptions_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

ReqOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

SramDwHasByteGranularity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

SramDwIsMultipleOfTlulWidth_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

TlOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

TlOutPayloadKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	5838977	0	0
T1	36336	124	0	0
T2	1494	0	0	0
T3	834762	16117	0	0
T4	107254	0	0	0
T5	4570	115	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	16135	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	546	0	0

TlOutPayloadKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WdataOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WeOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

WmaskOutKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

adapterNoReadOrWrite

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

rvalidHighReqFifoEmpty

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	4586078	0	0
T1	36336	124	0	0
T2	1494	0	0	0
T3	834762	16117	0	0
T4	107254	0	0	0
T5	4570	115	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	16135	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0

rvalidHighWhenRspFifoFull

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	4586078	0	0
T1	36336	124	0	0
T2	1494	0	0	0
T3	834762	16117	0	0
T4	107254	0	0	0
T5	4570	115	0	0
T15	4780	4	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	16135	0	0
T22	0	18	0	0
T23	0	6	0	0
T24	0	6	0	0
T31	0	16400	0	0
T39	0	291	0	0