Module Definition
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Module Instance : tb.dut.u_to_prog_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
84.25 100.00 66.67 84.62 85.71


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.71 89.33 66.13 82.14 81.25


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 87.32 100.00 74.29 75.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 69.33 91.43 57.14 68.75 60.00
u_sram_byte 100.00 100.00
u_sramreqfifo 72.63 94.44 54.84 81.25 60.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_to_rd_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.86 100.00 79.13 96.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.22 88.89 78.07 100.00 89.16 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 66.91 76.92 65.71 25.00 100.00
u_reqfifo 92.36 100.00 75.00 94.44 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 98.30 100.00 91.49 100.00 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 91.67 100.00 72.22 94.44 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00



Module Instance : tb.dut.u_tl_adapter_eflash

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.41 100.00 85.34 96.30 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.45 92.71 85.02 100.00 94.51 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.34 97.12 92.80 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_cmd_intg_check.u_cmd_intg_chk 100.00 100.00 100.00 100.00
u_err 81.79 100.00 77.14 50.00 100.00
u_reqfifo 96.53 100.00 86.11 100.00 100.00
u_rsp_gen 100.00 100.00 100.00
u_rspfifo 97.16 100.00 88.64 100.00 100.00
u_sram_byte 100.00 100.00
u_sramreqfifo 96.53 100.00 86.11 100.00 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00

Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
84.25 100.00
tb.dut.u_to_prog_fifo

Line No.TotalCoveredPercent
TOTAL6161100.00
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40800
CONT_ASSIGN41000
CONT_ASSIGN41700
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 unreachable
410 unreachable
417 unreachable
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
93.86 100.00
tb.dut.u_to_rd_fifo

Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41711100.00
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 1 1
410 1 1
417 1 1
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Line Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Line Coverage for Module self-instances :
SCORELINE
95.41 100.00
tb.dut.u_tl_adapter_eflash

Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41711100.00
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 1 1
410 1 1
417 1 1
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=0,ErrOnRead=1,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
84.25 66.67
tb.dut.u_to_prog_fifo

TotalCoveredPercent
Conditions1117466.67
Logical1117466.67
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T15,T17
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T15
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T15
11CoveredT1,T4,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T15,T20
11CoveredT1,T4,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T27
11CoveredT1,T4,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T15
1Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T15
1Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T15
11Not Covered

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T20,T27
101CoveredT1,T4,T15
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T5,T18
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T15
110Not Covered
111CoveredT1,T4,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T4,T15

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T15

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T15
11Not Covered

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T15
10Unreachable
11Unreachable

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=1,SramDw=32,Outstanding=1,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=0,EnableRspIntgGen=0,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=1,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
93.86 79.13
tb.dut.u_to_rd_fifo

TotalCoveredPercent
Conditions1159179.13
Logical1159179.13
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T36
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T14,T36
010CoveredT13,T14,T36
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T15,T17
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T15,T20
11CoveredT1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T2,T3

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T2,T3

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT56,T57,T13

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT56,T57,T13
11CoveredT1,T2,T3

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT56,T57,T13

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T5
101CoveredT20,T27,T44
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT20,T27,T44
10Not Covered
11CoveredT1,T2,T3

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : tlul_adapter_sram ( parameter SramAw=18,SramDw=32,Outstanding=2,ByteAccess=0,ErrOnWrite=1,ErrOnRead=0,CmdIntgCheck=1,EnableRspIntgGen=1,EnableDataIntgGen=0,EnableDataIntgPt=1,SecFifoPtr=0,WidthMult=1,DataOutW=39,DataBitWidth=2,WoffsetWidth=1,DataWidth=39 )
Cond Coverage for Module self-instances :
SCORECOND
95.41 85.34
tb.dut.u_tl_adapter_eflash

TotalCoveredPercent
Conditions1169985.34
Logical1169985.34
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT56,T57,T58

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT56,T57,T58
010Unreachable
100CoveredT56,T57,T58

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T15
01CoveredT1,T3,T16
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T16

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T9
01CoveredT1,T3,T16
10CoveredT1,T3,T16

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T3,T16
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T3,T16
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T3,T15
000001CoveredT58
000010CoveredT1,T3,T16
000100CoveredT39,T59,T60
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T21
11CoveredT1,T3,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T3,T15

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6,T57
1CoveredT1,T3,T15

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T3,T15
01CoveredT39,T56,T59
10CoveredT33,T61,T62

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT39,T56,T59
1110Not Covered
1111CoveredT1,T3,T15

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT33,T61,T62
11CoveredT1,T3,T15

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT39,T56,T59
10CoveredT1,T3,T15
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT57

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT57

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T15
11CoveredT39,T33,T61

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T3,T5
101CoveredT37,T45,T46
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T3,T5
01CoveredT1,T2,T3
10CoveredT1,T3,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T5
110CoveredT39,T56,T59
111CoveredT1,T3,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T3,T15
1Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T15
11Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T15

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10Not Covered
11CoveredT1,T3,T15

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T56,T59
11CoveredT1,T3,T15

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 326 2 2 100.00
TERNARY 449 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 359 2 2 100.00
IF 371 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 449 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T56,T6,T57
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T39,T56,T59
1 0 1 Covered T1,T2,T3
1 0 0 Covered T1,T4,T15
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T4,T15
0 - Covered T1,T2,T3


LineNo. Expression -1-: 359 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 1306798905 1304187372 0 0
DataIntgOptions_A 3186 3186 0 0
ReqOutKnown_A 1306798905 1304187372 0 0
SramDwHasByteGranularity_A 3186 3186 0 0
SramDwIsMultipleOfTlulWidth_A 3186 3186 0 0
TlOutKnown_A 1306798905 1304187372 0 0
TlOutPayloadKnown_A 1306798905 14305225 0 0
TlOutPayloadKnown_AKnownEnable 1306798905 1304187372 0 0
WdataOutKnown_A 1306798905 1304187372 0 0
WeOutKnown_A 1306798905 1304187372 0 0
WmaskOutKnown_A 1306798905 1304187372 0 0
adapterNoReadOrWrite 3186 3186 0 0
rvalidHighReqFifoEmpty 1306798905 7884093 0 0
rvalidHighWhenRspFifoFull 1306216973 7877496 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3186 3186 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3186 3186 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 3186 3186 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 14305225 0 0
T1 109008 2216 0 0
T2 4482 12 0 0
T3 2504286 29557 0 0
T4 321762 9216 0 0
T5 13710 169 0 0
T15 14340 552 0 0
T16 477132 4408 0 0
T17 9717 0 0 0
T18 5694 32 0 0
T19 1490976 18784 0 0
T20 0 26973 0 0
T21 0 16135 0 0
T22 0 178 0 0
T23 0 96 0 0
T24 0 22 0 0
T31 0 16400 0 0
T39 0 546 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 1304187372 0 0
T1 109008 108771 0 0
T2 4482 4293 0 0
T3 2504286 2503767 0 0
T4 321762 321612 0 0
T5 13710 13533 0 0
T15 14340 13917 0 0
T16 477132 448422 0 0
T17 9717 9498 0 0
T18 5694 5280 0 0
T19 1490976 1490949 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 3186 3186 0 0
T1 3 3 0 0
T2 3 3 0 0
T3 3 3 0 0
T4 3 3 0 0
T5 3 3 0 0
T15 3 3 0 0
T16 3 3 0 0
T17 3 3 0 0
T18 3 3 0 0
T19 3 3 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306798905 7884093 0 0
T1 72672 1265 0 0
T2 2988 12 0 0
T3 1669524 29557 0 0
T4 214508 4096 0 0
T5 9140 127 0 0
T15 9560 309 0 0
T16 318088 2896 0 0
T17 6478 0 0 0
T18 3796 0 0 0
T19 993984 0 0 0
T20 0 4096 0 0
T21 0 16135 0 0
T22 0 178 0 0
T23 0 80 0 0
T24 0 6 0 0
T31 0 16400 0 0
T39 0 291 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 1306216973 7877496 0 0
T1 72672 1265 0 0
T2 2988 12 0 0
T3 1669524 29557 0 0
T4 214508 4096 0 0
T5 9140 127 0 0
T15 9560 309 0 0
T16 318088 2896 0 0
T17 6478 0 0 0
T18 3796 0 0 0
T19 993984 0 0 0
T20 0 4096 0 0
T21 0 16135 0 0
T22 0 178 0 0
T23 0 80 0 0
T24 0 6 0 0
T31 0 16400 0 0
T39 0 291 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
TOTAL6161100.00
ALWAYS9433100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12611100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40800
CONT_ASSIGN41000
CONT_ASSIGN41700
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 unreachable
MISSING_ELSE
103 1 1
108 1 1
115 1 1
126 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 unreachable
410 unreachable
417 unreachable
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Cond Coverage for Instance : tb.dut.u_to_prog_fifo
TotalCoveredPercent
Conditions1117466.67
Logical1117466.67
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Unreachable
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T15,T17
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       126
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T4,T15
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Not Covered
010000Unreachable
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T15
11CoveredT1,T4,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T15,T20
11CoveredT1,T4,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T20,T27
11CoveredT1,T4,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T15
1Not Covered

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT1,T4,T15
1Not Covered

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111Not Covered

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T4,T15
11Not Covered

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT5,T20,T27
101CoveredT1,T4,T15
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T5,T18
01CoveredT1,T2,T3
10CoveredT1,T4,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T4,T15
110Not Covered
111CoveredT1,T4,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T15

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T4,T15

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T4,T15

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T15
11Not Covered

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T4,T15
10Unreachable
11Unreachable

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_to_prog_fifo
Line No.TotalCoveredPercent
Branches 26 22 84.62
TERNARY 108 2 2 100.00
TERNARY 293 2 1 50.00
TERNARY 299 3 1 33.33
TERNARY 326 2 2 100.00
TERNARY 449 2 1 50.00
IF 94 2 2 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 359 2 2 100.00
IF 371 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 449 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T6
1 0 1 Covered T6
1 0 0 Covered T1,T4,T15
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T6
1 0 Covered T1,T4,T15
0 - Covered T1,T2,T3


LineNo. Expression -1-: 359 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T4,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T6
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_prog_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 12 85.71
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 12 85.71




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 435599635 434729124 0 0
DataIntgOptions_A 1062 1062 0 0
ReqOutKnown_A 435599635 434729124 0 0
SramDwHasByteGranularity_A 1062 1062 0 0
SramDwIsMultipleOfTlulWidth_A 1062 1062 0 0
TlOutKnown_A 435599635 434729124 0 0
TlOutPayloadKnown_A 435599635 3581913 0 0
TlOutPayloadKnown_AKnownEnable 435599635 434729124 0 0
WdataOutKnown_A 435599635 434729124 0 0
WeOutKnown_A 435599635 434729124 0 0
WmaskOutKnown_A 435599635 434729124 0 0
adapterNoReadOrWrite 1062 1062 0 0
rvalidHighReqFifoEmpty 435599635 0 0 0
rvalidHighWhenRspFifoFull 435599635 0 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3581913 0 0
T1 36336 951 0 0
T2 1494 0 0 0
T3 834762 0 0 0
T4 107254 5120 0 0
T5 4570 42 0 0
T15 4780 243 0 0
T16 159044 1512 0 0
T17 3239 0 0 0
T18 1898 32 0 0
T19 496992 18784 0 0
T20 0 14068 0 0
T23 0 16 0 0
T24 0 16 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 0 0 0

Line Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41711100.00
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 1 1
410 1 1
417 1 1
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Cond Coverage for Instance : tb.dut.u_to_rd_fifo
TotalCoveredPercent
Conditions1159179.13
Logical1159179.13
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T36
10Unreachable

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT13,T14,T36
010CoveredT13,T14,T36
100Unreachable

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT4,T15,T17
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T2,T3
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T15,T20
11CoveredT1,T2,T3

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T5
11CoveredT1,T2,T3

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T2,T3

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T2,T3

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT56,T57,T13

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT1,T2,T3

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT56,T57,T13
11CoveredT1,T2,T3

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT56,T57,T13

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T2,T5
101CoveredT20,T27,T44
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T2,T5
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT20,T27,T44
10Not Covered
11CoveredT1,T2,T3

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_to_rd_fifo
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 326 2 2 100.00
TERNARY 449 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 359 2 2 100.00
IF 371 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 449 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T13,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T6
1 0 1 Covered T1,T2,T3
1 0 0 Covered T6
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T6
0 - Covered T1,T2,T3


LineNo. Expression -1-: 359 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_to_rd_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 435599635 434729124 0 0
DataIntgOptions_A 1062 1062 0 0
ReqOutKnown_A 435599635 434729124 0 0
SramDwHasByteGranularity_A 1062 1062 0 0
SramDwIsMultipleOfTlulWidth_A 1062 1062 0 0
TlOutKnown_A 435599635 434729124 0 0
TlOutPayloadKnown_A 435599635 4884335 0 0
TlOutPayloadKnown_AKnownEnable 435599635 434729124 0 0
WdataOutKnown_A 435599635 434729124 0 0
WeOutKnown_A 435599635 434729124 0 0
WmaskOutKnown_A 435599635 434729124 0 0
adapterNoReadOrWrite 1062 1062 0 0
rvalidHighReqFifoEmpty 435599635 3298015 0 0
rvalidHighWhenRspFifoFull 435017703 3291418 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4884335 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 12905 0 0
T22 0 160 0 0
T23 0 74 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 3298015 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 4096 0 0
T22 0 160 0 0
T23 0 74 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 435017703 3291418 0 0
T1 36336 1141 0 0
T2 1494 12 0 0
T3 834762 13440 0 0
T4 107254 4096 0 0
T5 4570 12 0 0
T15 4780 305 0 0
T16 159044 2896 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 0 4096 0 0
T22 0 160 0 0
T23 0 74 0 0

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
TOTAL6565100.00
ALWAYS9444100.00
CONT_ASSIGN10311100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN11511100.00
CONT_ASSIGN12011100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN22411100.00
CONT_ASSIGN22511100.00
CONT_ASSIGN22611100.00
ALWAYS23188100.00
ALWAYS25166100.00
CONT_ASSIGN26511100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN30311100.00
CONT_ASSIGN32311100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
ALWAYS35666100.00
ALWAYS36855100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN38011100.00
CONT_ASSIGN38911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40311100.00
CONT_ASSIGN40711100.00
CONT_ASSIGN40811100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41711100.00
ALWAYS42333100.00
CONT_ASSIGN44411100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45400
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
95 1 1
96 1 1
97 1 1
MISSING_ELSE
103 1 1
108 1 1
115 1 1
120 1 1
140 1 1
152 1 1
224 1 1
225 1 1
226 1 1
231 1 1
233 1 1
234 1 1
236 1 1
237 1 1
238 1 1
241 1 1
244 1 1
251 1 1
253 1 1
254 1 1
255 1 1
257 1 1
260 1 1
265 1 1
269 1 1
288 1 1
293 1 1
299 1 1
303 1 1
323 1 1
324 1 1
325 1 1
326 1 1
356 1 1
357 1 1
359 1 1
360 1 1
361 1 1
362 1 1
MISSING_ELSE
368 1 1
369 1 1
371 1 1
372 1 1
373 1 1
MISSING_ELSE
379 1 1
380 1 1
389 1 1
390 1 1
392 1 1
393 1 1
400 1 1
403 1 1
407 1 1
408 1 1
410 1 1
417 1 1
423 1 1
427 1 1
429 1 1
MISSING_ELSE
444 1 1
449 1 1
454 unreachable


Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalCoveredPercent
Conditions1169985.34
Logical1169985.34
Non-Logical00
Event00

 LINE       96
 EXPRESSION (intg_error || rsp_fifo_error)
             -----1----    -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT56,T57,T58

 LINE       103
 EXPRESSION (intg_error | rsp_fifo_error | intg_error_q)
             -----1----   -------2------   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT56,T57,T58
010Unreachable
100CoveredT56,T57,T58

 LINE       108
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T3,T15
01CoveredT1,T3,T16
10CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T16

 LINE       108
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T3,T9
01CoveredT1,T3,T16
10CoveredT1,T3,T16

 LINE       108
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T3,T16
1CoveredT1,T2,T3

 LINE       108
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T3,T16
1CoveredT1,T2,T3

 LINE       120
 EXPRESSION (tl_i.a_opcode != Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT1,T3,T15
000001CoveredT58
000010CoveredT1,T3,T16
000100CoveredT39,T59,T60
001000Unreachable
010000Not Covered
100000Not Covered

 LINE       224
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       225
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T21
11CoveredT1,T3,T15

 LINE       226
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       237
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6
1CoveredT1,T3,T15

 LINE       254
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT6,T57
1CoveredT1,T3,T15

 LINE       255
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT1,T3,T15
01CoveredT39,T56,T59
10CoveredT33,T61,T62

 LINE       265
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101CoveredT39,T56,T59
1110Not Covered
1111CoveredT1,T3,T15

 LINE       265
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       293
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       293
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT33,T61,T62
11CoveredT1,T3,T15

 LINE       299
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01CoveredT39,T56,T59
10CoveredT1,T3,T15
11Not Covered

 LINE       299
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT57

 LINE       303
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT57

 LINE       303
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       303
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T15
11CoveredT39,T33,T61

 LINE       303
 EXPRESSION ((gnt_i | error_internal) & reqfifo_wready & sramreqfifo_wready)
             ------------1-----------   -------2------   ---------3--------
-1--2--3-StatusTests
011CoveredT1,T3,T5
101CoveredT37,T45,T46
110Not Covered
111CoveredT1,T2,T3

 LINE       303
 SUB-EXPRESSION (gnt_i | error_internal)
                 --1--   -------2------
-1--2-StatusTests
00CoveredT1,T3,T5
01CoveredT1,T2,T3
10CoveredT1,T3,T15

 LINE       323
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T3,T5
110CoveredT39,T56,T59
111CoveredT1,T3,T15

 LINE       325
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11Not Covered

 LINE       326
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       362
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT1,T3,T15
1Not Covered

 LINE       362
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T15
11Not Covered

 LINE       393
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T15

 LINE       410
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10Not Covered
11CoveredT1,T3,T15

 LINE       449
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       449
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT39,T56,T59
11CoveredT1,T3,T15

 LINE       449
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash
Line No.TotalCoveredPercent
Branches 27 26 96.30
TERNARY 108 2 2 100.00
TERNARY 293 2 2 100.00
TERNARY 299 3 2 66.67
TERNARY 326 2 2 100.00
TERNARY 449 2 2 100.00
IF 94 3 3 100.00
IF 233 4 4 100.00
IF 253 3 3 100.00
IF 359 2 2 100.00
IF 371 2 2 100.00
IF 427 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 108 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T3,T15


LineNo. Expression -1-: 293 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 299 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 299 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T1,T3,T15
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 326 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 449 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 94 if ((!rst_ni)) -2-: 96 if ((intg_error || rsp_fifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T56,T6,T57
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 233 if (reqfifo_rvalid) -2-: 234 if (reqfifo_rdata.error) -3-: 237 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Covered T39,T56,T59
1 0 1 Covered T1,T3,T15
1 0 0 Covered T6
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 253 if (reqfifo_rvalid) -2-: 254 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T1,T3,T15
1 0 Covered T6,T57
0 - Covered T1,T2,T3


LineNo. Expression -1-: 359 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 371 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 427 if ((|sramreqfifo_rdata.mask))

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 14 14 100.00 14 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 14 14 100.00 14 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 435599635 434729124 0 0
DataIntgOptions_A 1062 1062 0 0
ReqOutKnown_A 435599635 434729124 0 0
SramDwHasByteGranularity_A 1062 1062 0 0
SramDwIsMultipleOfTlulWidth_A 1062 1062 0 0
TlOutKnown_A 435599635 434729124 0 0
TlOutPayloadKnown_A 435599635 5838977 0 0
TlOutPayloadKnown_AKnownEnable 435599635 434729124 0 0
WdataOutKnown_A 435599635 434729124 0 0
WeOutKnown_A 435599635 434729124 0 0
WmaskOutKnown_A 435599635 434729124 0 0
adapterNoReadOrWrite 1062 1062 0 0
rvalidHighReqFifoEmpty 435599635 4586078 0 0
rvalidHighWhenRspFifoFull 435599635 4586078 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

TlOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

TlOutPayloadKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 5838977 0 0
T1 36336 124 0 0
T2 1494 0 0 0
T3 834762 16117 0 0
T4 107254 0 0 0
T5 4570 115 0 0
T15 4780 4 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 16135 0 0
T22 0 18 0 0
T23 0 6 0 0
T24 0 6 0 0
T31 0 16400 0 0
T39 0 546 0 0

TlOutPayloadKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4586078 0 0
T1 36336 124 0 0
T2 1494 0 0 0
T3 834762 16117 0 0
T4 107254 0 0 0
T5 4570 115 0 0
T15 4780 4 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 16135 0 0
T22 0 18 0 0
T23 0 6 0 0
T24 0 6 0 0
T31 0 16400 0 0
T39 0 291 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 4586078 0 0
T1 36336 124 0 0
T2 1494 0 0 0
T3 834762 16117 0 0
T4 107254 0 0 0
T5 4570 115 0 0
T15 4780 4 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 16135 0 0
T22 0 18 0 0
T23 0 6 0 0
T24 0 6 0 0
T31 0 16400 0 0
T39 0 291 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%