Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.36 100.00 83.96 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.43 97.92 92.57 96.90 100.00 99.24 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 98.65 100.00 96.92 95.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 91.95 75.93 91.89 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.57 99.17 93.18 100.00 99.28 96.23
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.30 100.00 88.68 100.00 97.83 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 97.92 93.49 100.00 100.00 99.24 97.94


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.89 97.67 84.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prog_data.u_prog 99.49 100.00 96.92 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_erase 97.22 100.00 88.89 100.00 100.00
u_host_arb 93.98 75.93 100.00 100.00 100.00
u_host_outstanding_cnt 100.00 100.00
u_rd 97.65 99.17 93.60 100.00 99.28 96.23
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Module : flash_phy_core
TotalCoveredPercent
Conditions1069488.68
Logical1069488.68
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT6,T180,T177

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT6,T180,T177

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110Not Covered
111CoveredT1,T3,T15

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T3,T5
101CoveredT1,T3,T15
110Not Covered
111CoveredT1,T3,T15

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT1,T3,T15

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT70,T71,T72
10CoveredT1,T2,T3
11CoveredT1,T3,T15

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T3,T5

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT4,T16,T5
11CoveredT1,T16,T5

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT52,T181,T182

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT52,T181,T182

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T2,T3
11CoveredT1,T16,T5

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T16,T5
10CoveredT1,T2,T3
11CoveredT4,T16,T5

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT63,T64,T49
10CoveredT4,T16,T5

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T15
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T15
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T36
10CoveredT13,T14,T36

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T16,T20

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T16,T20

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T16,T20

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T16,T20

FSM Coverage for Module : flash_phy_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T4,T16,T5
StCtrlProg 338 Covered T1,T16,T5
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T9,T10,T11
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T4,T16,T5
StCtrlProg->StIdle 358 Covered T1,T16,T5
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T4,T16,T5
StIdle->StCtrlProg 338 Covered T1,T16,T5
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T9,T10,T11



Branch Coverage for Module : flash_phy_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T5
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T180,T177
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T3,T15


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T9,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T16,T5
StIdle 0 0 0 1 - - - Covered T4,T16,T5
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T16,T5
StCtrlProg - - - - - 0 - Covered T1,T16,T5
StCtrl - - - - - - 1 Covered T4,T16,T5
StCtrl - - - - - - 0 Covered T4,T16,T5
StDisable - - - - - - - Covered T9,T10,T11
default - - - - - - - Covered T6,T13,T14


Assert Coverage for Module : flash_phy_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 871199270 4348532 0 0
CtrlPrio_A 871199270 4348532 0 0
HostTransIdleChk_A 871199270 46268217 0 0
NoRemainder_A 2124 2124 0 0
OneHotReqs_A 871199270 869458248 0 0
Pow2Multiple_A 2124 2124 0 0
RdTxnCheck_A 870865544 869124522 0 0
u_state_regs_A 871199270 869458248 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 871199270 4348532 0 0
T1 36336 64 0 0
T2 1494 0 0 0
T3 1669524 91361 0 0
T4 214508 0 0 0
T5 9140 84 0 0
T15 9560 0 0 0
T16 318088 0 0 0
T17 6478 0 0 0
T18 3796 0 0 0
T19 993984 0 0 0
T20 143028 0 0 0
T21 0 2916 0 0
T28 0 487 0 0
T31 0 3232 0 0
T32 0 28119 0 0
T33 0 1786 0 0
T38 1705 0 0 0
T40 0 2705 0 0
T50 0 5649 0 0
T63 0 84 0 0
T112 0 3345 0 0
T167 0 3465 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 871199270 4348532 0 0
T1 36336 64 0 0
T2 1494 0 0 0
T3 1669524 91361 0 0
T4 214508 0 0 0
T5 9140 84 0 0
T15 9560 0 0 0
T16 318088 0 0 0
T17 6478 0 0 0
T18 3796 0 0 0
T19 993984 0 0 0
T20 143028 0 0 0
T21 0 2916 0 0
T28 0 487 0 0
T31 0 3232 0 0
T32 0 28119 0 0
T33 0 1786 0 0
T38 1705 0 0 0
T40 0 2705 0 0
T50 0 5649 0 0
T63 0 84 0 0
T112 0 3345 0 0
T167 0 3465 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 871199270 46268217 0 0
T1 72672 319 0 0
T2 2988 0 0 0
T3 1669524 821967 0 0
T4 214508 0 0 0
T5 9140 758 0 0
T15 9560 8 0 0
T16 318088 0 0 0
T17 6478 0 0 0
T18 3796 0 0 0
T19 993984 0 0 0
T21 0 54044 0 0
T22 0 44 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 44155 0 0
T33 0 16888 0 0
T39 0 448 0 0
T40 0 33122 0 0
T42 0 12 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2124 2124 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 871199270 869458248 0 0
T1 72672 72514 0 0
T2 2988 2862 0 0
T3 1669524 1669178 0 0
T4 214508 214408 0 0
T5 9140 9022 0 0
T15 9560 9278 0 0
T16 318088 298948 0 0
T17 6478 6332 0 0
T18 3796 3520 0 0
T19 993984 993966 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2124 2124 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T15 2 2 0 0
T16 2 2 0 0
T17 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 870865544 869124522 0 0
T1 72672 72514 0 0
T2 2988 2862 0 0
T3 1669524 1669178 0 0
T4 214508 214408 0 0
T5 9140 9022 0 0
T15 9560 9278 0 0
T16 318088 298948 0 0
T17 6478 6332 0 0
T18 3796 3520 0 0
T19 993984 993966 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 871199270 869458248 0 0
T1 72672 72514 0 0
T2 2988 2862 0 0
T3 1669524 1669178 0 0
T4 214508 214408 0 0
T5 9140 9022 0 0
T15 9560 9278 0 0
T16 318088 298948 0 0
T17 6478 6332 0 0
T18 3796 3520 0 0
T19 993984 993966 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalCoveredPercent
Conditions1068983.96
Logical1068983.96
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11Not Covered

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T3,T5
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T3,T5
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T3,T5
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110Not Covered
111CoveredT1,T3,T5

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T3,T5
101CoveredT1,T3,T5
110Not Covered
111CoveredT1,T3,T5

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T3,T5
11CoveredT3,T5,T31

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T18
11CoveredT1,T3,T5

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT41,T68,T69
11CoveredT1,T5,T18

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T18
11CoveredT1,T3,T5

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T3,T5
11CoveredT1,T5,T18

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T16,T5
10CoveredT1,T3,T5
11CoveredT41,T68,T69

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT63,T64,T49
10CoveredT4,T16,T5

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T5
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T5,T18
11CoveredT1,T3,T5

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T5
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T36
10CoveredT13,T14,T36

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T23,T24
10CoveredT1,T23,T43

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T23,T24
10CoveredT1,T23,T43

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T23,T43

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T23,T43

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T41,T68,T69
StCtrlProg 338 Covered T1,T5,T18
StCtrlRead 336 Covered T1,T3,T5
StDisable 334 Covered T9,T10,T11
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T41,T68,T69
StCtrlProg->StIdle 358 Covered T1,T5,T18
StCtrlRead->StIdle 348 Covered T1,T3,T5
StIdle->StCtrl 340 Covered T41,T68,T69
StIdle->StCtrlProg 338 Covered T1,T5,T18
StIdle->StCtrlRead 336 Covered T1,T3,T5
StIdle->StDisable 334 Covered T9,T10,T11



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T5
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T23,T43
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T23,T43
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T3,T5
0 0 1 Covered T3,T5,T31
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T3,T5


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T3,T5


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T9,T10,T11
StIdle 0 1 - - - - - Covered T1,T3,T5
StIdle 0 0 1 - - - - Covered T1,T5,T18
StIdle 0 0 0 1 - - - Covered T41,T68,T69
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T3,T5
StCtrlRead - - - - 0 - - Covered T1,T3,T5
StCtrlProg - - - - - 1 - Covered T1,T5,T18
StCtrlProg - - - - - 0 - Covered T1,T5,T18
StCtrl - - - - - - 1 Covered T41,T68,T69
StCtrl - - - - - - 0 Covered T41,T68,T69
StDisable - - - - - - - Covered T9,T10,T11
default - - - - - - - Covered T6,T13,T14


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 435599635 2131727 0 0
CtrlPrio_A 435599635 2131727 0 0
HostTransIdleChk_A 435599635 23590270 0 0
NoRemainder_A 1062 1062 0 0
OneHotReqs_A 435599635 434729124 0 0
Pow2Multiple_A 1062 1062 0 0
RdTxnCheck_A 435432772 434562261 0 0
u_state_regs_A 435599635 434729124 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 2131727 0 0
T3 834762 56547 0 0
T4 107254 0 0 0
T5 4570 0 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 143028 0 0 0
T21 0 936 0 0
T28 0 487 0 0
T31 0 1642 0 0
T32 0 28119 0 0
T33 0 355 0 0
T38 1705 0 0 0
T40 0 1355 0 0
T50 0 5649 0 0
T112 0 1660 0 0
T167 0 1005 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 2131727 0 0
T3 834762 56547 0 0
T4 107254 0 0 0
T5 4570 0 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T20 143028 0 0 0
T21 0 936 0 0
T28 0 487 0 0
T31 0 1642 0 0
T32 0 28119 0 0
T33 0 355 0 0
T38 1705 0 0 0
T40 0 1355 0 0
T50 0 5649 0 0
T112 0 1660 0 0
T167 0 1005 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 23590270 0 0
T1 36336 148 0 0
T2 1494 0 0 0
T3 834762 423606 0 0
T4 107254 0 0 0
T5 4570 223 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 26974 0 0
T23 0 24 0 0
T24 0 15 0 0
T31 0 24826 0 0
T33 0 16888 0 0
T39 0 249 0 0
T40 0 16104 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435432772 434562261 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
TOTAL8989100.00
ALWAYS15166100.00
ALWAYS16433100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19911100.00
ALWAYS20244100.00
ALWAYS21466100.00
ALWAYS22866100.00
CONT_ASSIGN27611100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28611100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32011100.00
ALWAYS3242929100.00
CONT_ASSIGN38711100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN39511100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN39711100.00
CONT_ASSIGN41411100.00
CONT_ASSIGN42711100.00
CONT_ASSIGN52111100.00
CONT_ASSIGN54811100.00
CONT_ASSIGN54911100.00
CONT_ASSIGN55011100.00
CONT_ASSIGN55111100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55511100.00
CONT_ASSIGN55611100.00
CONT_ASSIGN55711100.00
CONT_ASSIGN55811100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56611100.00
CONT_ASSIGN58311100.00
CONT_ASSIGN58411100.00
CONT_ASSIGN58511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
151 1 1
152 1 1
153 1 1
154 1 1
155 1 1
156 1 1
MISSING_ELSE
164 3 3
195 1 1
199 1 1
202 1 1
203 1 1
204 1 1
205 1 1
MISSING_ELSE
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
MISSING_ELSE
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
233 1 1
MISSING_ELSE
276 1 1
279 1 1
280 1 1
281 1 1
286 1 1
316 1 1
320 1 1
324 1 1
325 1 1
326 1 1
327 1 1
328 1 1
330 1 1
332 1 1
333 1 1
334 1 1
335 1 1
336 1 1
337 1 1
338 1 1
339 1 1
340 1 1
MISSING_ELSE
346 1 1
347 1 1
348 1 1
MISSING_ELSE
355 1 1
356 1 1
357 1 1
358 1 1
MISSING_ELSE
364 1 1
365 1 1
366 1 1
367 1 1
368 1 1
MISSING_ELSE
373 1 1
374 1 1
387 1 1
391 1 1
392 1 1
393 1 1
394 1 1
395 1 1
396 1 1
397 1 1
414 1 1
427 1 1
521 1 1
548 1 1
549 1 1
550 1 1
551 1 1
553 1 1
554 1 1
555 1 1
556 1 1
557 1 1
558 1 1
559 1 1
566 1 1
583 1 1
584 1 1
585 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalCoveredPercent
Conditions1069488.68
Logical1069488.68
Non-Logical00
Event00

 LINE       195
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT6,T180,T177

 LINE       195
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       199
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11Not Covered

 LINE       204
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT6,T180,T177

 LINE       216
 EXPRESSION (host_outstanding == '0)
            ------------1-----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       230
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       230
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T3,T15
1CoveredT1,T2,T3

 LINE       241
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110Not Covered
111CoveredT1,T3,T15

 LINE       241
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------
-1--2--3-StatusTests
011CoveredT1,T3,T5
101CoveredT1,T3,T15
110Not Covered
111CoveredT1,T3,T15

 LINE       280
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T3,T5
11CoveredT1,T3,T15

 LINE       281
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T15
11CoveredT1,T3,T15

 LINE       316
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       316
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---
-1--2-StatusTests
01CoveredT70,T71,T72
10CoveredT1,T2,T3
11CoveredT1,T3,T15

 LINE       320
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11CoveredT1,T3,T5

 LINE       335
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       337
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--
-1--2-StatusTests
01CoveredT1,T5,T18
10CoveredT4,T16,T5
11CoveredT1,T16,T5

 LINE       387
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT52,T181,T182

 LINE       387
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT52,T181,T182

 LINE       387
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------
-1--2-StatusTests
01CoveredT1,T3,T15
10CoveredT1,T2,T3
11Not Covered

 LINE       387
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       391
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       392
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       393
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       394
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       395
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       396
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--
-1--2-StatusTests
01CoveredT1,T16,T5
10CoveredT1,T2,T3
11CoveredT1,T16,T5

 LINE       397
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------
-1--2-StatusTests
01CoveredT4,T16,T5
10CoveredT1,T2,T3
11CoveredT4,T16,T5

 LINE       397
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT63,T64,T49
10CoveredT4,T16,T5

 LINE       427
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       427
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------
-1--2-StatusTests
01CoveredT1,T3,T15
10Not Covered
11Not Covered

 LINE       427
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T15

 LINE       430
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T16
11CoveredT1,T2,T3

 LINE       430
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T15
10CoveredT1,T2,T3

 LINE       430
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       521
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T14,T36
10CoveredT13,T14,T36

 LINE       548
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T16,T20

 LINE       549
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T16,T20

 LINE       550
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T16,T20

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T16,T20

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StCtrl 340 Covered T4,T16,T5
StCtrlProg 338 Covered T1,T16,T5
StCtrlRead 336 Covered T1,T2,T3
StDisable 334 Covered T9,T11,T12
StIdle 348 Covered T1,T2,T3


transitionsLine No.CoveredTests
StCtrl->StIdle 368 Covered T4,T16,T5
StCtrlProg->StIdle 358 Covered T1,T16,T5
StCtrlRead->StIdle 348 Covered T1,T2,T3
StIdle->StCtrl 340 Covered T4,T16,T5
StIdle->StCtrlProg 338 Covered T1,T16,T5
StIdle->StCtrlRead 336 Covered T1,T2,T3
StIdle->StDisable 334 Covered T9,T11,T12



Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
Line No.TotalCoveredPercent
Branches 46 45 97.83
TERNARY 316 2 2 100.00
TERNARY 391 2 2 100.00
TERNARY 392 2 2 100.00
TERNARY 393 2 2 100.00
TERNARY 394 2 2 100.00
TERNARY 550 2 2 100.00
TERNARY 551 2 2 100.00
TERNARY 430 2 1 50.00
IF 151 4 4 100.00
IF 164 2 2 100.00
IF 202 3 3 100.00
IF 214 4 4 100.00
IF 228 4 4 100.00
CASE 330 13 13 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 316 ((phy_req & host_req)) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 391 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 392 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 394 (host_sel) ?

Branches:
-1-StatusTests
1 Covered T1,T3,T15
0 Covered T1,T2,T3


LineNo. Expression -1-: 550 (prog_op_req) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 551 (prog_calc_req) ?

Branches:
-1-StatusTests
1 Covered T1,T16,T20
0 Covered T1,T2,T3


LineNo. Expression -1-: 430 (arb_host_gnt_err) ?

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


LineNo. Expression -1-: 151 if ((!rst_ni)) -2-: 153 if (ctrl_rsp_vld) -3-: 155 if (inc_arb_cnt)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T3,T5
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 164 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 202 if ((!rst_ni)) -2-: 204 if ((host_gnt_err_event | host_outstanding_err_event))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T180,T177
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 214 if ((!rst_ni)) -2-: 216 if ((host_outstanding == '0)) -3-: 218 if (host_gnt_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T3,T15


LineNo. Expression -1-: 228 if ((!rst_ni)) -2-: 230 if (((host_outstanding == '0) && ctrl_fsm_idle)) -3-: 232 if (host_outstanding_err_event)

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 330 case (state_q) -2-: 333 if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx])) -3-: 335 if ((ctrl_gnt && rd_i)) -4-: 337 if ((ctrl_gnt && prog_i)) -5-: 339 if (ctrl_gnt) -6-: 346 if (rd_stage_data_valid) -7-: 356 if (prog_ack) -8-: 366 if (erase_ack)

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T9,T10,T11
StIdle 0 1 - - - - - Covered T1,T2,T3
StIdle 0 0 1 - - - - Covered T1,T16,T5
StIdle 0 0 0 1 - - - Covered T4,T16,T5
StIdle 0 0 0 0 - - - Covered T1,T2,T3
StCtrlRead - - - - 1 - - Covered T1,T2,T3
StCtrlRead - - - - 0 - - Covered T1,T2,T3
StCtrlProg - - - - - 1 - Covered T1,T16,T5
StCtrlProg - - - - - 0 - Covered T1,T16,T5
StCtrl - - - - - - 1 Covered T4,T16,T5
StCtrl - - - - - - 0 Covered T4,T16,T5
StDisable - - - - - - - Covered T9,T11,T12
default - - - - - - - Covered T6,T13,T14


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 8 8 100.00 8 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 8 8 100.00 8 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
ArbCntMax_A 435599635 2216805 0 0
CtrlPrio_A 435599635 2216805 0 0
HostTransIdleChk_A 435599635 22677947 0 0
NoRemainder_A 1062 1062 0 0
OneHotReqs_A 435599635 434729124 0 0
Pow2Multiple_A 1062 1062 0 0
RdTxnCheck_A 435432772 434562261 0 0
u_state_regs_A 435599635 434729124 0 0


ArbCntMax_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 2216805 0 0
T1 36336 64 0 0
T2 1494 0 0 0
T3 834762 34814 0 0
T4 107254 0 0 0
T5 4570 84 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 1980 0 0
T31 0 1590 0 0
T33 0 1431 0 0
T40 0 1350 0 0
T63 0 84 0 0
T112 0 1685 0 0
T167 0 2460 0 0

CtrlPrio_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 2216805 0 0
T1 36336 64 0 0
T2 1494 0 0 0
T3 834762 34814 0 0
T4 107254 0 0 0
T5 4570 84 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 1980 0 0
T31 0 1590 0 0
T33 0 1431 0 0
T40 0 1350 0 0
T63 0 84 0 0
T112 0 1685 0 0
T167 0 2460 0 0

HostTransIdleChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 22677947 0 0
T1 36336 171 0 0
T2 1494 0 0 0
T3 834762 398361 0 0
T4 107254 0 0 0
T5 4570 535 0 0
T15 4780 8 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 27070 0 0
T22 0 44 0 0
T31 0 19329 0 0
T39 0 199 0 0
T40 0 17018 0 0
T42 0 12 0 0

NoRemainder_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

OneHotReqs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

Pow2Multiple_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1062 1062 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T15 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0

RdTxnCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435432772 434562261 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 434729124 0 0
T1 36336 36257 0 0
T2 1494 1431 0 0
T3 834762 834589 0 0
T4 107254 107204 0 0
T5 4570 4511 0 0
T15 4780 4639 0 0
T16 159044 149474 0 0
T17 3239 3166 0 0
T18 1898 1760 0 0
T19 496992 496983 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%