Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1742398540	1738916496	0	0
CheckNGreaterZero_A	4248	4248	0	0
GntImpliesReady_A	1742398540	454725183	0	0
GntImpliesValid_A	1742398540	454725183	0	0
GrantKnown_A	1742398540	1738916496	0	0
IdxKnown_A	1742398540	1738916496	0	0
IndexIsCorrect_A	1742398540	454725183	0	0
NoReadyValidNoGrant_A	1742398540	179928196	0	0
Priority_A	1742398540	479291449	0	0
ReadyAndValidImplyGrant_A	1742398540	454725183	0	0
ReqAndReadyImplyGrant_A	1742398540	454725183	0	0
ReqImpliesValid_A	1742398540	479291449	0	0
ValidKnown_A	1742398540	1738916496	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	1738916496	0	0
T1	145344	145028	0	0
T2	5976	5724	0	0
T3	3339048	3338356	0	0
T4	429016	428816	0	0
T5	18280	18044	0	0
T15	19120	18556	0	0
T16	636176	597896	0	0
T17	12956	12664	0	0
T18	7592	7040	0	0
T19	1987968	1987932	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4248	4248	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0
T19	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	454725183	0	0
T1	145344	47782	0	0
T2	5976	88	0	0
T3	3339048	59184	0	0
T4	429016	584	0	0
T5	18280	3406	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	17096	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	32650	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	454725183	0	0
T1	145344	47782	0	0
T2	5976	88	0	0
T3	3339048	59184	0	0
T4	429016	584	0	0
T5	18280	3406	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	17096	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	32650	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	1738916496	0	0
T1	145344	145028	0	0
T2	5976	5724	0	0
T3	3339048	3338356	0	0
T4	429016	428816	0	0
T5	18280	18044	0	0
T15	19120	18556	0	0
T16	636176	597896	0	0
T17	12956	12664	0	0
T18	7592	7040	0	0
T19	1987968	1987932	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	1738916496	0	0
T1	145344	145028	0	0
T2	5976	5724	0	0
T3	3339048	3338356	0	0
T4	429016	428816	0	0
T5	18280	18044	0	0
T15	19120	18556	0	0
T16	636176	597896	0	0
T17	12956	12664	0	0
T18	7592	7040	0	0
T19	1987968	1987932	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	454725183	0	0
T1	145344	47782	0	0
T2	5976	88	0	0
T3	3339048	59184	0	0
T4	429016	584	0	0
T5	18280	3406	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	17096	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	32650	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	179928196	0	0
T1	145344	5182	0	0
T2	5976	292	0	0
T3	3339048	1847702	0	0
T4	429016	128	0	0
T5	18280	1760	0	0
T15	19120	992	0	0
T16	636176	46352	0	0
T17	12956	256	0	0
T18	7592	512	0	0
T19	1987968	3392	0	0
T21	0	48702	0	0
T23	0	388	0	0
T24	0	278	0	0
T31	0	64616	0	0
T39	0	1366	0	0
T40	0	30378	0	0
T41	0	214566	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	479291449	0	0
T1	145344	47788	0	0
T2	5976	88	0	0
T3	3339048	619062	0	0
T4	429016	584	0	0
T5	18280	3866	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	18088	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	36170	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	454725183	0	0
T1	145344	47782	0	0
T2	5976	88	0	0
T3	3339048	59184	0	0
T4	429016	584	0	0
T5	18280	3406	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	17096	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	32650	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	454725183	0	0
T1	145344	47782	0	0
T2	5976	88	0	0
T3	3339048	59184	0	0
T4	429016	584	0	0
T5	18280	3406	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	17096	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	32650	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	479291449	0	0
T1	145344	47788	0	0
T2	5976	88	0	0
T3	3339048	619062	0	0
T4	429016	584	0	0
T5	18280	3866	0	0
T15	19120	428	0	0
T16	636176	198320	0	0
T17	12956	64	0	0
T18	7592	364	0	0
T19	1987968	989004	0	0
T21	0	18088	0	0
T23	0	1024	0	0
T24	0	1264	0	0
T25	0	316372	0	0
T31	0	36170	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1742398540	1738916496	0	0
T1	145344	145028	0	0
T2	5976	5724	0	0
T3	3339048	3338356	0	0
T4	429016	428816	0	0
T5	18280	18044	0	0
T15	19120	18556	0	0
T16	636176	597896	0	0
T17	12956	12664	0	0
T18	7592	7040	0	0
T19	1987968	1987932	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435599635	434729124	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	435599635	114449450	0	0
GntImpliesValid_A	435599635	114449450	0	0
GrantKnown_A	435599635	434729124	0	0
IdxKnown_A	435599635	434729124	0	0
IndexIsCorrect_A	435599635	114449450	0	0
NoReadyValidNoGrant_A	435599635	45712262	0	0
Priority_A	435599635	120630736	0	0
ReadyAndValidImplyGrant_A	435599635	114449450	0	0
ReqAndReadyImplyGrant_A	435599635	114449450	0	0
ReqImpliesValid_A	435599635	120630736	0	0
ValidKnown_A	435599635	434729124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114449450	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114449450	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114449450	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	45712262	0	0
T1	36336	1227	0	0
T2	1494	146	0	0
T3	834762	425571	0	0
T4	107254	64	0	0
T5	4570	639	0	0
T15	4780	496	0	0
T16	159044	23176	0	0
T17	3239	128	0	0
T18	1898	256	0	0
T19	496992	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	120630736	0	0
T1	36336	9129	0	0
T2	1494	44	0	0
T3	834762	143210	0	0
T4	107254	292	0	0
T5	4570	1693	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114449450	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114449450	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	120630736	0	0
T1	36336	9129	0	0
T2	1494	44	0	0
T3	834762	143210	0	0
T4	107254	292	0	0
T5	4570	1693	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T15
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T15

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T15
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T15

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435599635	434729124	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	435599635	114214229	0	0
GntImpliesValid_A	435599635	114214229	0	0
GrantKnown_A	435599635	434729124	0	0
IdxKnown_A	435599635	434729124	0	0
IndexIsCorrect_A	435599635	114214229	0	0
NoReadyValidNoGrant_A	435599635	45712264	0	0
Priority_A	435599635	120395513	0	0
ReadyAndValidImplyGrant_A	435599635	114214229	0	0
ReqAndReadyImplyGrant_A	435599635	114214229	0	0
ReqImpliesValid_A	435599635	120395513	0	0
ValidKnown_A	435599635	434729124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114214229	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114214229	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114214229	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	45712264	0	0
T1	36336	1227	0	0
T2	1494	146	0	0
T3	834762	425571	0	0
T4	107254	64	0	0
T5	4570	639	0	0
T15	4780	496	0	0
T16	159044	23176	0	0
T17	3239	128	0	0
T18	1898	256	0	0
T19	496992	1696	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	120395513	0	0
T1	36336	9129	0	0
T2	1494	44	0	0
T3	834762	143210	0	0
T4	107254	292	0	0
T5	4570	1693	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114214229	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	114214229	0	0
T1	36336	9128	0	0
T2	1494	44	0	0
T3	834762	13366	0	0
T4	107254	292	0	0
T5	4570	1508	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	120395513	0	0
T1	36336	9129	0	0
T2	1494	44	0	0
T3	834762	143210	0	0
T4	107254	292	0	0
T5	4570	1693	0	0
T15	4780	214	0	0
T16	159044	99160	0	0
T17	3239	32	0	0
T18	1898	64	0	0
T19	496992	290233	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435599635	434729124	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	435599635	113030752	0	0
GntImpliesValid_A	435599635	113030752	0	0
GrantKnown_A	435599635	434729124	0	0
IdxKnown_A	435599635	434729124	0	0
IndexIsCorrect_A	435599635	113030752	0	0
NoReadyValidNoGrant_A	435599635	44251835	0	0
Priority_A	435599635	119132600	0	0
ReadyAndValidImplyGrant_A	435599635	113030752	0	0
ReqAndReadyImplyGrant_A	435599635	113030752	0	0
ReqImpliesValid_A	435599635	119132600	0	0
ValidKnown_A	435599635	434729124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	44251835	0	0
T1	36336	1364	0	0
T2	1494	0	0	0
T3	834762	498280	0	0
T4	107254	0	0	0
T5	4570	241	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	24351	0	0
T23	0	194	0	0
T24	0	139	0	0
T31	0	32308	0	0
T39	0	683	0	0
T40	0	15189	0	0
T41	0	107283	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	119132600	0	0
T1	36336	14765	0	0
T2	1494	0	0	0
T3	834762	166321	0	0
T4	107254	0	0	0
T5	4570	240	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	9044	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	18085	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	119132600	0	0
T1	36336	14765	0	0
T2	1494	0	0	0
T3	834762	166321	0	0
T4	107254	0	0	0
T5	4570	240	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	9044	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	18085	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T3,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T5

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	435599635	434729124	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	435599635	113030752	0	0
GntImpliesValid_A	435599635	113030752	0	0
GrantKnown_A	435599635	434729124	0	0
IdxKnown_A	435599635	434729124	0	0
IndexIsCorrect_A	435599635	113030752	0	0
NoReadyValidNoGrant_A	435599635	44251835	0	0
Priority_A	435599635	119132600	0	0
ReadyAndValidImplyGrant_A	435599635	113030752	0	0
ReqAndReadyImplyGrant_A	435599635	113030752	0	0
ReqImpliesValid_A	435599635	119132600	0	0
ValidKnown_A	435599635	434729124	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	44251835	0	0
T1	36336	1364	0	0
T2	1494	0	0	0
T3	834762	498280	0	0
T4	107254	0	0	0
T5	4570	241	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	0	0	0
T19	496992	0	0	0
T21	0	24351	0	0
T23	0	194	0	0
T24	0	139	0	0
T31	0	32308	0	0
T39	0	683	0	0
T40	0	15189	0	0
T41	0	107283	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	119132600	0	0
T1	36336	14765	0	0
T2	1494	0	0	0
T3	834762	166321	0	0
T4	107254	0	0	0
T5	4570	240	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	9044	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	18085	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	113030752	0	0
T1	36336	14763	0	0
T2	1494	0	0	0
T3	834762	16226	0	0
T4	107254	0	0	0
T5	4570	195	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	8548	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	16325	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	119132600	0	0
T1	36336	14765	0	0
T2	1494	0	0	0
T3	834762	166321	0	0
T4	107254	0	0	0
T5	4570	240	0	0
T15	4780	0	0	0
T16	159044	0	0	0
T17	3239	0	0	0
T18	1898	118	0	0
T19	496992	204269	0	0
T21	0	9044	0	0
T23	0	512	0	0
T24	0	632	0	0
T25	0	158186	0	0
T31	0	18085	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	435599635	434729124	0	0
T1	36336	36257	0	0
T2	1494	1431	0	0
T3	834762	834589	0	0
T4	107254	107204	0	0
T5	4570	4511	0	0
T15	4780	4639	0	0
T16	159044	149474	0	0
T17	3239	3166	0	0
T18	1898	1760	0	0
T19	496992	496983	0	0