Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.74 100.00 90.97 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.74 100.00 90.97 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.74 100.00 90.97 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.74 100.00 90.97 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.47 100.00 89.87 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.47 100.00 89.87 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.47 100.00 89.87 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.64 100.00 78.57 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.47 100.00 89.87 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Module : flash_phy_rd_buffers
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT79,T80,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T5,T22

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Module : flash_phy_rd_buffers
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T79,T80,T81
0 0 1 - - Covered T16,T5,T22
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_phy_rd_buffers
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 2147483647 5737009 0 0
UpdateCheck_A 2147483647 5736991 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5737009 0 0
T1 290688 499 0 0
T2 11952 6 0 0
T3 6678096 23607 0 0
T4 858032 0 0 0
T5 36560 68 0 0
T15 38240 38 0 0
T16 1272352 1384 0 0
T17 25912 0 0 0
T18 15184 0 0 0
T19 3975936 0 0 0
T21 0 17333 0 0
T22 0 109 0 0
T23 0 42 0 0
T24 0 44 0 0
T31 0 26162 0 0
T33 0 9053 0 0
T39 0 452 0 0
T40 0 9941 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 5736991 0 0
T1 290688 499 0 0
T2 11952 6 0 0
T3 6678096 23607 0 0
T4 858032 0 0 0
T5 36560 68 0 0
T15 38240 38 0 0
T16 1272352 1384 0 0
T17 25912 0 0 0
T18 15184 0 0 0
T19 3975936 0 0 0
T21 0 17333 0 0
T22 0 109 0 0
T23 0 42 0 0
T24 0 44 0 0
T31 0 26162 0 0
T33 0 9053 0 0
T39 0 452 0 0
T40 0 9941 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT79,T80,T81

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T22,T82

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T79,T80,T81
0 0 1 - - Covered T16,T22,T82
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 657795 0 0
UpdateCheck_A 435599635 657792 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657795 0 0
T1 36336 56 0 0
T2 1494 2 0 0
T3 834762 2720 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 10 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2248 0 0
T22 0 30 0 0
T31 0 3415 0 0
T39 0 52 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657792 0 0
T1 36336 56 0 0
T2 1494 2 0 0
T3 834762 2720 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 10 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2248 0 0
T22 0 30 0 0
T31 0 3415 0 0
T39 0 52 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT79,T81,T66

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T22,T42

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T79,T81,T6
0 0 1 - - Covered T16,T22,T42
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 657441 0 0
UpdateCheck_A 435599635 657436 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657441 0 0
T1 36336 56 0 0
T2 1494 2 0 0
T3 834762 2724 0 0
T4 107254 0 0 0
T5 4570 10 0 0
T15 4780 10 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2242 0 0
T22 0 28 0 0
T31 0 3413 0 0
T39 0 51 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657436 0 0
T1 36336 56 0 0
T2 1494 2 0 0
T3 834762 2724 0 0
T4 107254 0 0 0
T5 4570 10 0 0
T15 4780 10 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2242 0 0
T22 0 28 0 0
T31 0 3413 0 0
T39 0 51 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT79,T81,T66

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T22,T42

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T79,T81,T6
0 0 1 - - Covered T16,T22,T42
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 657326 0 0
UpdateCheck_A 435599635 657323 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657326 0 0
T1 36336 56 0 0
T2 1494 1 0 0
T3 834762 2714 0 0
T4 107254 0 0 0
T5 4570 10 0 0
T15 4780 9 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2249 0 0
T22 0 24 0 0
T31 0 3406 0 0
T39 0 51 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657323 0 0
T1 36336 56 0 0
T2 1494 1 0 0
T3 834762 2714 0 0
T4 107254 0 0 0
T5 4570 10 0 0
T15 4780 9 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2249 0 0
T22 0 24 0 0
T31 0 3406 0 0
T39 0 51 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT79,T81,T66

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT16,T5,T22

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T79,T81,T6
0 0 1 - - Covered T16,T5,T22
0 0 0 1 - Covered T1,T2,T3
0 0 0 0 1 Covered T1,T2,T3
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 657054 0 0
UpdateCheck_A 435599635 657052 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657054 0 0
T1 36336 57 0 0
T2 1494 1 0 0
T3 834762 2723 0 0
T4 107254 0 0 0
T5 4570 11 0 0
T15 4780 9 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2247 0 0
T22 0 27 0 0
T31 0 3398 0 0
T39 0 51 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 657052 0 0
T1 36336 57 0 0
T2 1494 1 0 0
T3 834762 2723 0 0
T4 107254 0 0 0
T5 4570 11 0 0
T15 4780 9 0 0
T16 159044 346 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2247 0 0
T22 0 27 0 0
T31 0 3398 0 0
T39 0 51 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT66,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT85,T86,T64

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T6,T66,T83
0 0 1 - - Covered T85,T86,T64
0 0 0 1 - Covered T1,T3,T5
0 0 0 0 1 Covered T1,T3,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 777250 0 0
UpdateCheck_A 435599635 777247 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 777250 0 0
T1 36336 69 0 0
T2 1494 0 0 0
T3 834762 3187 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2089 0 0
T23 0 11 0 0
T24 0 11 0 0
T31 0 3137 0 0
T33 0 2286 0 0
T39 0 62 0 0
T40 0 2486 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 777247 0 0
T1 36336 69 0 0
T2 1494 0 0 0
T3 834762 3187 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2089 0 0
T23 0 11 0 0
T24 0 11 0 0
T31 0 3137 0 0
T33 0 2286 0 0
T39 0 62 0 0
T40 0 2486 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT66,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT43,T34,T85

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T6,T66,T83
0 0 1 - - Covered T43,T34,T85
0 0 0 1 - Covered T1,T3,T5
0 0 0 0 1 Covered T1,T3,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 776892 0 0
UpdateCheck_A 435599635 776892 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776892 0 0
T1 36336 69 0 0
T2 1494 0 0 0
T3 834762 3171 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2087 0 0
T23 0 11 0 0
T24 0 11 0 0
T31 0 3129 0 0
T33 0 2246 0 0
T39 0 62 0 0
T40 0 2480 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776892 0 0
T1 36336 69 0 0
T2 1494 0 0 0
T3 834762 3171 0 0
T4 107254 0 0 0
T5 4570 8 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2087 0 0
T23 0 11 0 0
T24 0 11 0 0
T31 0 3129 0 0
T33 0 2246 0 0
T39 0 62 0 0
T40 0 2480 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT66,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT43,T85,T86

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T6,T66,T83
0 0 1 - - Covered T43,T85,T86
0 0 0 1 - Covered T1,T3,T5
0 0 0 0 1 Covered T1,T3,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 776737 0 0
UpdateCheck_A 435599635 776736 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776737 0 0
T1 36336 68 0 0
T2 1494 0 0 0
T3 834762 3186 0 0
T4 107254 0 0 0
T5 4570 6 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2085 0 0
T23 0 10 0 0
T24 0 10 0 0
T31 0 3132 0 0
T33 0 2257 0 0
T39 0 62 0 0
T40 0 2481 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776736 0 0
T1 36336 68 0 0
T2 1494 0 0 0
T3 834762 3186 0 0
T4 107254 0 0 0
T5 4570 6 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2085 0 0
T23 0 10 0 0
T24 0 10 0 0
T31 0 3132 0 0
T33 0 2257 0 0
T39 0 62 0 0
T40 0 2481 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
TOTAL2323100.00
ALWAYS382323100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
38 1 1
39 1 1
40 1 1
41 1 1
42 1 1
43 1 1
44 1 1
45 1 1
46 1 1
47 1 1
48 1 1
49 1 1
50 1 1
51 1 1
52 1 1
53 1 1
54 1 1
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalCoveredPercent
Conditions141178.57
Logical141178.57
Non-Logical00
Event00

 LINE       45
 EXPRESSION (((!en_i)) && (out_o.attr != Invalid))
             ----1----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T3,T5
10CoveredT1,T2,T3
11CoveredT66,T83,T84

 LINE       45
 SUB-EXPRESSION (out_o.attr != Invalid)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       48
 EXPRESSION (wipe_i && en_i)
             ---1--    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT24,T85,T86

 LINE       51
 EXPRESSION (alloc_i && en_i)
             ---1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

 LINE       57
 EXPRESSION (update_i && en_i)
             ----1---    --2-
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T5

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
Line No.TotalCoveredPercent
Branches 6 6 100.00
IF 38 6 6 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 38 if ((!rst_ni)) -2-: 45 if (((!en_i) && (out_o.attr != Invalid))) -3-: 48 if ((wipe_i && en_i)) -4-: 51 if ((alloc_i && en_i)) -5-: 57 if ((update_i && en_i))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T6,T66,T83
0 0 1 - - Covered T24,T85,T86
0 0 0 1 - Covered T1,T3,T5
0 0 0 0 1 Covered T1,T3,T5
0 0 0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllocCheck_A 435599635 776514 0 0
UpdateCheck_A 435599635 776513 0 0


AllocCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776514 0 0
T1 36336 68 0 0
T2 1494 0 0 0
T3 834762 3182 0 0
T4 107254 0 0 0
T5 4570 7 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2086 0 0
T23 0 10 0 0
T24 0 12 0 0
T31 0 3132 0 0
T33 0 2264 0 0
T39 0 61 0 0
T40 0 2494 0 0

UpdateCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 435599635 776513 0 0
T1 36336 68 0 0
T2 1494 0 0 0
T3 834762 3182 0 0
T4 107254 0 0 0
T5 4570 7 0 0
T15 4780 0 0 0
T16 159044 0 0 0
T17 3239 0 0 0
T18 1898 0 0 0
T19 496992 0 0 0
T21 0 2086 0 0
T23 0 10 0 0
T24 0 12 0 0
T31 0 3132 0 0
T33 0 2264 0 0
T39 0 61 0 0
T40 0 2494 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%