Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26832766	1		T1	122		T2	64		T3	3886
full_word	7929246	1		T1	2		T2	42		T3	24395

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34761712	1		T1	124		T2	106		T3	28281
auto[TlIntgErrCmd]	103	1		T199	1		T233	5		T255	5
auto[TlIntgErrData]	105	1		T199	6		T233	2		T255	7
auto[TlIntgErrBoth]	92	1		T199	3		T233	3		T255	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30307814	1		T1	115		T2	59		T3	3580
auto[1]	4454198	1		T1	9		T2	47		T3	24701

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26165474	1		T1	115		T2	59		T3	1765
auto[TlIntgErrNone]	partial	auto[1]	667012	1		T1	7		T2	5		T3	2121
auto[TlIntgErrNone]	full_word	auto[0]	4142224	1		T3	1815		T4	59		T5	1176
auto[TlIntgErrNone]	full_word	auto[1]	3787002	1		T1	2		T2	42		T3	22580
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T233	2		T255	2		T300	3
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T199	1		T233	3		T255	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T274	1		T357	1		T359	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1		T278	1		T360	1		T361	1
auto[TlIntgErrData]	partial	auto[0]	38	1		T199	4		T255	4		T300	3
auto[TlIntgErrData]	partial	auto[1]	57	1		T199	2		T233	2		T255	3
auto[TlIntgErrData]	full_word	auto[0]	8	1		T355	1		T274	1		T362	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T355	1		T361	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	27	1		T233	2		T255	2		T355	4
auto[TlIntgErrBoth]	partial	auto[1]	61	1		T199	3		T233	1		T255	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T255	1		T363	1		T364	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T361	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18842	1		T197	59		T198	176		T200	1283
full_word	4469076	1		T4	139		T8	16407		T9	99

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4487646	1		T4	139		T8	16407		T9	99
auto[TlIntgErrCmd]	89	1		T199	3		T233	3		T255	10
auto[TlIntgErrData]	87	1		T199	2		T233	4		T255	2
auto[TlIntgErrBoth]	96	1		T199	5		T233	2		T255	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4464073	1		T4	139		T8	16407		T9	99
auto[1]	23845	1		T197	72		T198	229		T200	1554

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1201	1		T197	5		T198	4		T200	69
auto[TlIntgErrNone]	partial	auto[1]	17391	1		T197	54		T198	172		T200	1214
auto[TlIntgErrNone]	full_word	auto[0]	4462761	1		T4	139		T8	16407		T9	99
auto[TlIntgErrNone]	full_word	auto[1]	6293	1		T197	18		T198	57		T200	340
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T255	3		T300	1		T355	6
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T199	3		T233	3		T255	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T355	1		T360	1		T359	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T255	2		T274	1		T364	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T199	1		T233	2		T300	4
auto[TlIntgErrData]	partial	auto[1]	41	1		T199	1		T233	2		T255	1
auto[TlIntgErrData]	full_word	auto[0]	2	1		T255	1		T279	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1		T276	1		T362	1		T278	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T233	1		T255	3		T300	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1		T199	1		T233	1		T255	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T199	2		T358	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1		T199	2		T255	1		T355	1