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Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.44 100.00 87.18 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.52 100.00 90.09 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.44 100.00 87.18 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.52 100.00 90.09 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.19 100.00 68.75 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 80.56 94.44 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.52 100.00 90.09 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 93.64 100.00 90.00 90.91

Go back
Module Instances:
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT8,T24,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT4,T5,T8
110Not Covered
111CoveredT4,T5,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T8
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T8


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412725974 50136493 0 0
DepthKnown_A 412725974 411928473 0 0
RvalidKnown_A 412725974 411928473 0 0
WreadyKnown_A 412725974 411928473 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412725974 50136493 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 50136493 0 0
T4 69976 272 0 0
T5 41411 188 0 0
T6 90346 0 0 0
T7 0 532186 0 0
T8 109662 41349 0 0
T9 69747 70 0 0
T13 1157 0 0 0
T16 515431 698 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 29533 0 0
T33 2324 219 0 0
T54 0 153 0 0
T60 0 524288 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 50136493 0 0
T4 69976 272 0 0
T5 41411 188 0 0
T6 90346 0 0 0
T7 0 532186 0 0
T8 109662 41349 0 0
T9 69747 70 0 0
T13 1157 0 0 0
T16 515431 698 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 29533 0 0
T33 2324 219 0 0
T54 0 153 0 0
T60 0 524288 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT15,T37,T56
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT4,T5,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT4,T5,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT5,T8,T24
110Not Covered
111CoveredT4,T5,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT4,T5,T8
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T4,T5,T8


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T4,T5,T8
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412725974 12882148 0 0
DepthKnown_A 412725974 411928473 0 0
RvalidKnown_A 412725974 411928473 0 0
WreadyKnown_A 412725974 411928473 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412725974 12882148 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 12882148 0 0
T4 69976 42 0 0
T5 41411 76 0 0
T6 90346 0 0 0
T7 0 10380 0 0
T8 109662 24275 0 0
T9 69747 25 0 0
T13 1157 0 0 0
T16 515431 245 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 13152 0 0
T33 2324 73 0 0
T54 0 70 0 0
T60 0 262144 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 411928473 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412725974 12882148 0 0
T4 69976 42 0 0
T5 41411 76 0 0
T6 90346 0 0 0
T7 0 10380 0 0
T8 109662 24275 0 0
T9 69747 25 0 0
T13 1157 0 0 0
T16 515431 245 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 13152 0 0
T33 2324 73 0 0
T54 0 70 0 0
T60 0 262144 0 0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T8,T54

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT5,T8,T54

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT4,T16,T9
101CoveredT5,T8,T24
110Not Covered
111CoveredT5,T8,T54

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT5,T8,T54
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T8,T54


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T5,T8,T54
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 412959766 11636494 0 0
DepthKnown_A 412959766 412162265 0 0
RvalidKnown_A 412959766 412162265 0 0
WreadyKnown_A 412959766 412162265 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 412959766 11636494 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412959766 11636494 0 0
T5 41411 76 0 0
T6 90346 0 0 0
T8 109662 20706 0 0
T9 69747 0 0 0
T13 1157 0 0 0
T16 515431 0 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 2966 0 0
T25 0 80 0 0
T33 2324 0 0 0
T34 0 5542 0 0
T51 0 104364 0 0
T54 0 9 0 0
T60 0 262144 0 0
T61 0 68080 0 0
T62 1138 0 0 0
T67 0 68 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412959766 412162265 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412959766 412162265 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 412959766 412162265 0 0
T1 3859 3251 0 0
T2 1189 922 0 0
T3 498265 498256 0 0
T4 69976 69876 0 0
T5 41411 41348 0 0
T6 90346 90263 0 0
T8 109662 109481 0 0
T9 69747 69676 0 0
T16 515431 515334 0 0
T17 2237 2141 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 412959766 11636494 0 0
T5 41411 76 0 0
T6 90346 0 0 0
T8 109662 20706 0 0
T9 69747 0 0 0
T13 1157 0 0 0
T16 515431 0 0 0
T17 2237 0 0 0
T23 4167 0 0 0
T24 0 2966 0 0
T25 0 80 0 0
T33 2324 0 0 0
T34 0 5542 0 0
T51 0 104364 0 0
T54 0 9 0 0
T60 0 262144 0 0
T61 0 68080 0 0
T62 1138 0 0 0
T67 0 68 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%