Module Definition
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Module : flash_ctrl_rd
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.29 100.00 93.94 100.00 95.24

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_rd 97.29 100.00 93.94 100.00 95.24



Module Instance : tb.dut.u_flash_ctrl_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.29 100.00 93.94 100.00 95.24


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.02 93.94 100.00 100.00 95.24


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.50 97.12 93.60 98.44 100.00 98.33 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_bus_intg 0.00 0.00
u_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_rd
Line No.TotalCoveredPercent
TOTAL4444100.00
ALWAYS5233100.00
ALWAYS6055100.00
ALWAYS9744100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
ALWAYS1132424100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN16511100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN18011100.00
CONT_ASSIGN18211100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 1 1
53 1 1
55 1 1
60 1 1
61 1 1
62 1 1
63 1 1
65 1 1
97 1 1
98 1 1
99 1 1
100 1 1
MISSING_ELSE
104 1 1
105 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
119 1 1
121 1 1
123 1 1
124 1 1
125 1 1
126 1 1
MISSING_ELSE
133 1 1
135 1 1
136 1 1
137 1 1
139 1 1
141 1 1
142 1 1
143 1 1
145 1 1
MISSING_ELSE
151 1 1
153 1 1
154 1 1
155 1 1
MISSING_ELSE
163 1 1
164 1 1
165 1 1
167 1 1
180 1 1
182 1 1


Cond Coverage for Module : flash_ctrl_rd
TotalCoveredPercent
Conditions333193.94
Logical333193.94
Non-Logical00
Event00

 LINE       62
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT14,T15,T166
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       71
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01CoveredT14,T15,T166
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       99
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01CoveredT1,T5,T16
10CoveredT1,T2,T3
11CoveredT1,T5,T16

 LINE       104
 EXPRESSION (flash_req_o & flash_done_i)
             -----1-----   ------2-----
-1--2-StatusTests
01CoveredT2,T3,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       126
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       133
 EXPRESSION (op_start_i & data_rdy_i)
             -----1----   -----2----
-1--2-StatusTests
01CoveredT2,T13,T62
10CoveredT19,T30,T185
11CoveredT1,T2,T3

 LINE       145
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T5,T16

 LINE       153
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01CoveredT6,T19,T30
10CoveredT1,T5,T16
11CoveredT1,T5,T16

 LINE       167
 EXPRESSION (data_wr_o & ((|op_err_o)))
             ----1----   ------2------
-1--2-StatusTests
01CoveredT6,T19,T30
10CoveredT1,T2,T3
11CoveredT1,T5,T16

 LINE       180
 EXPRESSION ((((~err_sel)) | (err_sel & op_err_o.rd_err)) ? flash_data_i : inv_data_integ)
             ----------------------1---------------------
-1-StatusTests
0CoveredT5,T16,T6
1CoveredT1,T2,T3

 LINE       180
 SUB-EXPRESSION (((~err_sel)) | (err_sel & op_err_o.rd_err))
                 ------1-----   -------------2-------------
-1--2-StatusTests
00CoveredT5,T16,T6
01CoveredT1,T79,T25
10CoveredT1,T2,T3

 LINE       180
 SUB-EXPRESSION (err_sel & op_err_o.rd_err)
                 ---1---   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT5,T16,T6
11CoveredT1,T79,T25

FSM Coverage for Module : flash_ctrl_rd
Summary for FSM :: st_q
TotalCoveredPercent
States 3 3 100.00 (Not included in score)
Transitions 5 5 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: st_q
statesLine No.CoveredTests
StErr 123 Covered T1,T5,T16
StIdle 143 Covered T1,T2,T3
StNorm 126 Covered T1,T2,T3


transitionsLine No.CoveredTests
StErr->StIdle 154 Covered T1,T5,T16
StIdle->StErr 123 Covered T14,T15,T37
StIdle->StNorm 126 Covered T1,T2,T3
StNorm->StErr 145 Covered T1,T5,T16
StNorm->StIdle 143 Covered T1,T2,T3



Branch Coverage for Module : flash_ctrl_rd
Line No.TotalCoveredPercent
Branches 21 20 95.24
TERNARY 180 2 2 100.00
IF 52 2 2 100.00
IF 60 3 3 100.00
IF 97 3 3 100.00
CASE 119 11 10 90.91

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_rd.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 180 (((~err_sel) | (err_sel & op_err_o.rd_err))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T5,T16,T6


LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 if ((!rst_ni)) -2-: 62 if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 97 if ((!rst_ni)) -2-: 99 if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T5,T16
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 119 case (st_q) -2-: 121 if (cnt_err_o) -3-: 124 if (op_start_i) -4-: 126 ((|op_err_d)) ? -5-: 135 if (txn_done) -6-: 141 if (cnt_hit) -7-: 145 ((|op_err_d)) ? -8-: 153 if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StIdle 1 - - - - - - Covered T11,T14,T15
StIdle 0 1 1 - - - - Not Covered
StIdle 0 1 0 - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - Covered T1,T2,T3
StNorm - - - 1 1 - - Covered T1,T2,T3
StNorm - - - 1 0 1 - Covered T1,T5,T16
StNorm - - - 1 0 0 - Covered T1,T2,T3
StNorm - - - 0 - - - Covered T1,T2,T3
StErr - - - - - - 1 Covered T1,T5,T16
StErr - - - - - - 0 Covered T1,T5,T16
default - - - - - - - Covered T11

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%