Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err

Group : cip_base_pkg::tl_intg_err_cg_wrap::tl_intg_err_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64
tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]	100.00	1	100	1	64	64

Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	0	2	100.00	100	1	1	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Group Instance : tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	100.00

Variables for Group Instance tl_intg_err_cgs_wrap[flash_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_mem	2	1	1	50.00	100	0	0	2
cp_num_cmd_err_bits	4	0	4	100.00	100	1	1	0
cp_num_data_err_bits	4	0	4	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	29223171	1	T1	106	T2	124884	T3	6324
auto[1]	5457313	1	T2	16304	T3	10672	T4	10514

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	34680310	1	T1	106	T2	141188	T3	16996
values[1]	11	1	T65	1	T192	4	T269	3
values[2]	3	1	T363	2	T364	1	-	-
values[3]	95	1	T63	8	T65	3	T192	2

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	34680308	1	T1	106	T2	141188	T3	16996
values[1]	17	1	T63	3	T65	1	T192	1
values[2]	4	1	T365	1	T366	1	T367	1
values[3]	82	1	T63	4	T65	4	T192	1

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[TlIntgErrNone]	34680214	1	T1	106	T2	141188	T3	16996
auto[TlIntgErrCmd]	94	1	T63	10	T65	4	T192	5
auto[TlIntgErrData]	96	1	T63	5	T65	4	T192	4
auto[TlIntgErrBoth]	80	1	T63	5	T65	2	T192	1

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
[auto[0]]	0	0	-	-	-	-	-	-
auto[1]	4489860	0	T2	37394	T3	16579	T4	41208

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	4489704	1	T2	37394	T3	16579	T4	41208
values[1]	18	1	T63	3	T250	1	T269	1
values[2]	1	1	T295	1	-	-	-	-
values[3]	75	1	T63	5	T65	5	T192	3

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	4489681	1	T2	37394	T3	16579	T4	41208
values[1]	20	1	T65	1	T192	2	T365	1
values[2]	5	1	T367	1	T368	1	T363	1
values[3]	81	1	T63	9	T192	2	T295	3

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[TlIntgErrNone]	4489608	1	T2	37394	T3	16579	T4	41208
auto[TlIntgErrCmd]	73	1	T63	6	T65	5	T192	2
auto[TlIntgErrData]	96	1	T63	8	T65	3	T192	6
auto[TlIntgErrBoth]	83	1	T63	6	T65	2	T192	1

Summary for Variable cp_is_mem

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_is_mem

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
[auto[1]]	0	0	-	-	-	-	-	-
auto[0]	83656	0	T63	1237	T191	2235	T65	635

Summary for Variable cp_num_cmd_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_cmd_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	83469	1	T63	1221	T191	2235	T65	630
values[1]	20	1	T63	2	T295	2	T269	1
values[2]	4	1	T269	1	T365	1	T366	1
values[3]	92	1	T63	9	T65	1	T192	5

Summary for Variable cp_num_data_err_bits

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_num_data_err_bits

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
values[0]	83474	1	T63	1223	T191	2235	T65	628
values[1]	19	1	T63	2	T295	1	T250	1
values[2]	3	1	T369	1	T370	1	T371	1
values[3]	86	1	T63	5	T65	2	T192	5

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[TlIntgErrNone]	83386	1	T63	1217	T191	2235	T65	625
auto[TlIntgErrCmd]	88	1	T63	6	T65	3	T192	3
auto[TlIntgErrData]	83	1	T63	4	T65	5	T192	3
auto[TlIntgErrBoth]	99	1	T63	10	T65	2	T192	4