Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	26634190	1		T1	64		T2	115069		T3	3900
full_word	8046294	1		T1	42		T2	26119		T3	13096

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34680214	1		T1	106		T2	141188		T3	16996
auto[TlIntgErrCmd]	94	1		T63	10		T65	4		T192	5
auto[TlIntgErrData]	96	1		T63	5		T65	4		T192	4
auto[TlIntgErrBoth]	80	1		T63	5		T65	2		T192	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30125190	1		T1	59		T2	126883		T3	14281
auto[1]	4555294	1		T1	47		T2	14305		T3	2715

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	25952403	1		T1	58		T2	112726		T3	2928
auto[TlIntgErrNone]	partial	auto[1]	681541	1		T1	6		T2	2343		T3	972
auto[TlIntgErrNone]	full_word	auto[0]	4172660	1		T1	1		T2	14157		T3	11353
auto[TlIntgErrNone]	full_word	auto[1]	3873610	1		T1	41		T2	11962		T3	1743
auto[TlIntgErrCmd]	partial	auto[0]	39	1		T63	3		T65	1		T192	3
auto[TlIntgErrCmd]	partial	auto[1]	50	1		T63	5		T65	3		T192	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T63	1		T365	1		T372	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T63	1		T371	1		-	-
auto[TlIntgErrData]	partial	auto[0]	39	1		T63	1		T192	4		T250	2
auto[TlIntgErrData]	partial	auto[1]	44	1		T63	3		T65	3		T295	1
auto[TlIntgErrData]	full_word	auto[0]	7	1		T63	1		T65	1		T372	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T269	1		T367	2		T368	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T63	1		T65	1		T192	1
auto[TlIntgErrBoth]	partial	auto[1]	40	1		T63	4		T65	1		T295	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T366	1		T363	1		T371	1
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T371	1		-	-		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	20460	1		T63	20		T65	9		T192	9
full_word	4469400	1		T2	37394		T3	16579		T4	41208

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4489608	1		T2	37394		T3	16579		T4	41208
auto[TlIntgErrCmd]	73	1		T63	6		T65	5		T192	2
auto[TlIntgErrData]	96	1		T63	8		T65	3		T192	6
auto[TlIntgErrBoth]	83	1		T63	6		T65	2		T192	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4463854	1		T2	37394		T3	16579		T4	41208
auto[1]	26006	1		T63	9		T65	6		T192	5

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1293	1		T216	1		T217	32		T218	83
auto[TlIntgErrNone]	partial	auto[1]	18934	1		T216	30		T217	420		T218	587
auto[TlIntgErrNone]	full_word	auto[0]	4462460	1		T2	37394		T3	16579		T4	41208
auto[TlIntgErrNone]	full_word	auto[1]	6921	1		T216	18		T217	288		T218	225
auto[TlIntgErrCmd]	partial	auto[0]	27	1		T63	4		T65	3		T192	1
auto[TlIntgErrCmd]	partial	auto[1]	40	1		T63	2		T65	1		T192	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T295	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T65	1		T366	1		T367	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T63	6		T65	1		T192	3
auto[TlIntgErrData]	partial	auto[1]	42	1		T63	2		T65	2		T192	3
auto[TlIntgErrData]	full_word	auto[0]	5	1		T250	2		T372	1		T366	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T367	1		T368	1		T373	1
auto[TlIntgErrBoth]	partial	auto[0]	20	1		T63	1		T250	1		T365	1
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T63	5		T65	2		T192	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T363	1		T374	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T295	1		T367	1		T370	1