Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1700307132	1696779860	0	0
CheckNGreaterZero_A	4248	4248	0	0
GntImpliesReady_A	1700307132	462675617	0	0
GntImpliesValid_A	1700307132	462675617	0	0
GrantKnown_A	1700307132	1696779860	0	0
IdxKnown_A	1700307132	1696779860	0	0
IndexIsCorrect_A	1700307132	462675617	0	0
NoReadyValidNoGrant_A	1700307132	180670111	0	0
Priority_A	1700307132	486696862	0	0
ReadyAndValidImplyGrant_A	1700307132	462675617	0	0
ReqAndReadyImplyGrant_A	1700307132	462675617	0	0
ReqImpliesValid_A	1700307132	486696862	0	0
ValidKnown_A	1700307132	1696779860	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	1696779860	0	0
T1	6116	5132	0	0
T2	1144388	1144124	0	0
T3	3116012	3115492	0	0
T4	1050560	1050356	0	0
T5	3964	3660	0	0
T9	14448	11908	0	0
T14	3289220	3288620	0	0
T15	16052	15612	0	0
T16	184008	183732	0	0
T17	439256	438876	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4248	4248	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T9	4	4	0	0
T14	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	462675617	0	0
T1	3058	134	0	0
T2	1144388	308414	0	0
T3	3116012	54584	0	0
T4	1050560	329676	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	58770	0	0
T15	16052	566	0	0
T16	184008	43172	0	0
T17	439256	124976	0	0
T19	0	968	0	0
T37	0	190464	0	0
T38	0	60598	0	0
T53	6426	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	462675617	0	0
T1	3058	134	0	0
T2	1144388	308414	0	0
T3	3116012	54584	0	0
T4	1050560	329676	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	58770	0	0
T15	16052	566	0	0
T16	184008	43172	0	0
T17	439256	124976	0	0
T19	0	968	0	0
T37	0	190464	0	0
T38	0	60598	0	0
T53	6426	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	1696779860	0	0
T1	6116	5132	0	0
T2	1144388	1144124	0	0
T3	3116012	3115492	0	0
T4	1050560	1050356	0	0
T5	3964	3660	0	0
T9	14448	11908	0	0
T14	3289220	3288620	0	0
T15	16052	15612	0	0
T16	184008	183732	0	0
T17	439256	438876	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	1696779860	0	0
T1	6116	5132	0	0
T2	1144388	1144124	0	0
T3	3116012	3115492	0	0
T4	1050560	1050356	0	0
T5	3964	3660	0	0
T9	14448	11908	0	0
T14	3289220	3288620	0	0
T15	16052	15612	0	0
T16	184008	183732	0	0
T17	439256	438876	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	462675617	0	0
T1	3058	134	0	0
T2	1144388	308414	0	0
T3	3116012	54584	0	0
T4	1050560	329676	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	58770	0	0
T15	16052	566	0	0
T16	184008	43172	0	0
T17	439256	124976	0	0
T19	0	968	0	0
T37	0	190464	0	0
T38	0	60598	0	0
T53	6426	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	180670111	0	0
T1	3058	536	0	0
T2	1144388	227856	0	0
T3	3116012	1792454	0	0
T4	1050560	193482	0	0
T5	3964	256	0	0
T9	14448	1344	0	0
T14	3289220	1933924	0	0
T15	16052	1554	0	0
T16	184008	55062	0	0
T17	439256	76626	0	0
T19	0	420	0	0
T37	0	88646	0	0
T38	0	65844	0	0
T53	6426	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	486696862	0	0
T1	3058	134	0	0
T2	1144388	387722	0	0
T3	3116012	577940	0	0
T4	1050560	409006	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	520120	0	0
T15	16052	566	0	0
T16	184008	54658	0	0
T17	439256	172040	0	0
T19	0	968	0	0
T37	0	231638	0	0
T38	0	74104	0	0
T53	6426	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	462675617	0	0
T1	3058	134	0	0
T2	1144388	308414	0	0
T3	3116012	54584	0	0
T4	1050560	329676	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	58770	0	0
T15	16052	566	0	0
T16	184008	43172	0	0
T17	439256	124976	0	0
T19	0	968	0	0
T37	0	190464	0	0
T38	0	60598	0	0
T53	6426	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	462675617	0	0
T1	3058	134	0	0
T2	1144388	308414	0	0
T3	3116012	54584	0	0
T4	1050560	329676	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	58770	0	0
T15	16052	566	0	0
T16	184008	43172	0	0
T17	439256	124976	0	0
T19	0	968	0	0
T37	0	190464	0	0
T38	0	60598	0	0
T53	6426	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	486696862	0	0
T1	3058	134	0	0
T2	1144388	387722	0	0
T3	3116012	577940	0	0
T4	1050560	409006	0	0
T5	3964	542	0	0
T9	14448	338	0	0
T14	3289220	520120	0	0
T15	16052	566	0	0
T16	184008	54658	0	0
T17	439256	172040	0	0
T19	0	968	0	0
T37	0	231638	0	0
T38	0	74104	0	0
T53	6426	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1700307132	1696779860	0	0
T1	6116	5132	0	0
T2	1144388	1144124	0	0
T3	3116012	3115492	0	0
T4	1050560	1050356	0	0
T5	3964	3660	0	0
T9	14448	11908	0	0
T14	3289220	3288620	0	0
T15	16052	15612	0	0
T16	184008	183732	0	0
T17	439256	438876	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425076783	424194965	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	425076783	122251205	0	0
GntImpliesValid_A	425076783	122251205	0	0
GrantKnown_A	425076783	424194965	0	0
IdxKnown_A	425076783	424194965	0	0
IndexIsCorrect_A	425076783	122251205	0	0
NoReadyValidNoGrant_A	425076783	46677057	0	0
Priority_A	425076783	128467775	0	0
ReadyAndValidImplyGrant_A	425076783	122251205	0	0
ReqAndReadyImplyGrant_A	425076783	122251205	0	0
ReqImpliesValid_A	425076783	128467775	0	0
ValidKnown_A	425076783	424194965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251205	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251205	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251205	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	46677057	0	0
T1	1529	268	0	0
T2	286097	60756	0	0
T3	779003	405880	0	0
T4	262640	51704	0	0
T5	991	128	0	0
T9	3612	672	0	0
T14	822305	524681	0	0
T15	4013	256	0	0
T16	46002	13292	0	0
T17	109814	23931	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	128467775	0	0
T1	1529	67	0	0
T2	286097	99207	0	0
T3	779003	117112	0	0
T4	262640	105706	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	139299	0	0
T15	4013	64	0	0
T16	46002	12033	0	0
T17	109814	54671	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251205	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251205	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	128467775	0	0
T1	1529	67	0	0
T2	286097	99207	0	0
T3	779003	117112	0	0
T4	262640	105706	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	139299	0	0
T15	4013	64	0	0
T16	46002	12033	0	0
T17	109814	54671	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425076783	424194965	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	425076783	122251189	0	0
GntImpliesValid_A	425076783	122251189	0	0
GrantKnown_A	425076783	424194965	0	0
IdxKnown_A	425076783	424194965	0	0
IndexIsCorrect_A	425076783	122251189	0	0
NoReadyValidNoGrant_A	425076783	46676994	0	0
Priority_A	425076783	128467822	0	0
ReadyAndValidImplyGrant_A	425076783	122251189	0	0
ReqAndReadyImplyGrant_A	425076783	122251189	0	0
ReqImpliesValid_A	425076783	128467822	0	0
ValidKnown_A	425076783	424194965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251189	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251189	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251189	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	46676994	0	0
T1	1529	268	0	0
T2	286097	60756	0	0
T3	779003	405880	0	0
T4	262640	51704	0	0
T5	991	128	0	0
T9	3612	672	0	0
T14	822305	524681	0	0
T15	4013	256	0	0
T16	46002	13292	0	0
T17	109814	23931	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	128467822	0	0
T1	1529	67	0	0
T2	286097	99207	0	0
T3	779003	117112	0	0
T4	262640	105706	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	139299	0	0
T15	4013	64	0	0
T16	46002	12033	0	0
T17	109814	54671	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251189	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	122251189	0	0
T1	1529	67	0	0
T2	286097	78619	0	0
T3	779003	11786	0	0
T4	262640	83589	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	16310	0	0
T15	4013	64	0	0
T16	46002	9881	0	0
T17	109814	34586	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	128467822	0	0
T1	1529	67	0	0
T2	286097	99207	0	0
T3	779003	117112	0	0
T4	262640	105706	0	0
T5	991	271	0	0
T9	3612	169	0	0
T14	822305	139299	0	0
T15	4013	64	0	0
T16	46002	12033	0	0
T17	109814	54671	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425076783	424194965	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	425076783	109086653	0	0
GntImpliesValid_A	425076783	109086653	0	0
GrantKnown_A	425076783	424194965	0	0
IdxKnown_A	425076783	424194965	0	0
IndexIsCorrect_A	425076783	109086653	0	0
NoReadyValidNoGrant_A	425076783	43658030	0	0
Priority_A	425076783	114880674	0	0
ReadyAndValidImplyGrant_A	425076783	109086653	0	0
ReqAndReadyImplyGrant_A	425076783	109086653	0	0
ReqImpliesValid_A	425076783	114880674	0	0
ValidKnown_A	425076783	424194965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086653	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086653	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086653	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	43658030	0	0
T2	286097	53172	0	0
T3	779003	490347	0	0
T4	262640	45037	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	442281	0	0
T15	4013	521	0	0
T16	46002	14239	0	0
T17	109814	14382	0	0
T19	0	210	0	0
T37	0	44323	0	0
T38	0	32922	0	0
T53	3213	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	114880674	0	0
T2	286097	94654	0	0
T3	779003	171858	0	0
T4	262640	98797	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	120761	0	0
T15	4013	219	0	0
T16	46002	15296	0	0
T17	109814	31349	0	0
T19	0	484	0	0
T37	0	115819	0	0
T38	0	37052	0	0
T53	3213	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086653	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086653	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	114880674	0	0
T2	286097	94654	0	0
T3	779003	171858	0	0
T4	262640	98797	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	120761	0	0
T15	4013	219	0	0
T16	46002	15296	0	0
T17	109814	31349	0	0
T19	0	484	0	0
T37	0	115819	0	0
T38	0	37052	0	0
T53	3213	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	425076783	424194965	0	0
CheckNGreaterZero_A	1062	1062	0	0
GntImpliesReady_A	425076783	109086570	0	0
GntImpliesValid_A	425076783	109086570	0	0
GrantKnown_A	425076783	424194965	0	0
IdxKnown_A	425076783	424194965	0	0
IndexIsCorrect_A	425076783	109086570	0	0
NoReadyValidNoGrant_A	425076783	43658030	0	0
Priority_A	425076783	114880591	0	0
ReadyAndValidImplyGrant_A	425076783	109086570	0	0
ReqAndReadyImplyGrant_A	425076783	109086570	0	0
ReqImpliesValid_A	425076783	114880591	0	0
ValidKnown_A	425076783	424194965	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1062	1062	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T9	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086570	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086570	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086570	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	43658030	0	0
T2	286097	53172	0	0
T3	779003	490347	0	0
T4	262640	45037	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	442281	0	0
T15	4013	521	0	0
T16	46002	14239	0	0
T17	109814	14382	0	0
T19	0	210	0	0
T37	0	44323	0	0
T38	0	32922	0	0
T53	3213	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	114880591	0	0
T2	286097	94654	0	0
T3	779003	171858	0	0
T4	262640	98797	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	120761	0	0
T15	4013	219	0	0
T16	46002	15296	0	0
T17	109814	31349	0	0
T19	0	484	0	0
T37	0	115819	0	0
T38	0	37052	0	0
T53	3213	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086570	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	109086570	0	0
T2	286097	75588	0	0
T3	779003	15506	0	0
T4	262640	81249	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	13075	0	0
T15	4013	219	0	0
T16	46002	11705	0	0
T17	109814	27902	0	0
T19	0	484	0	0
T37	0	95232	0	0
T38	0	30299	0	0
T53	3213	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	114880591	0	0
T2	286097	94654	0	0
T3	779003	171858	0	0
T4	262640	98797	0	0
T5	991	0	0	0
T9	3612	0	0	0
T14	822305	120761	0	0
T15	4013	219	0	0
T16	46002	15296	0	0
T17	109814	31349	0	0
T19	0	484	0	0
T37	0	115819	0	0
T38	0	37052	0	0
T53	3213	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	425076783	424194965	0	0
T1	1529	1283	0	0
T2	286097	286031	0	0
T3	779003	778873	0	0
T4	262640	262589	0	0
T5	991	915	0	0
T9	3612	2977	0	0
T14	822305	822155	0	0
T15	4013	3903	0	0
T16	46002	45933	0	0
T17	109814	109719	0	0