Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	27115934	1		T1	733		T2	107		T3	19
full_word	7817171	1		T1	2328		T2	4		T3	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	34932805	1		T1	3061		T2	111		T3	20
auto[TlIntgErrCmd]	108	1		T63	2		T65	12		T236	5
auto[TlIntgErrData]	90	1		T63	3		T65	3		T236	2
auto[TlIntgErrBoth]	102	1		T63	5		T65	5		T236	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30422223	1		T1	1099		T2	103		T3	19
auto[1]	4510882	1		T1	1962		T2	8		T3	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	26453862	1		T1	579		T2	102		T3	18
auto[TlIntgErrNone]	partial	auto[1]	661798	1		T1	154		T2	5		T3	1
auto[TlIntgErrNone]	full_word	auto[0]	3968234	1		T1	520		T2	1		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	3848911	1		T1	1808		T2	3		T4	17122
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T63	2		T65	7		T236	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1		T65	5		T218	6		T219	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T219	1		T252	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T236	1		T354	1		T258	1
auto[TlIntgErrData]	partial	auto[0]	39	1		T65	2		T236	2		T218	1
auto[TlIntgErrData]	partial	auto[1]	44	1		T63	2		T65	1		T218	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T63	1		T357	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T219	1		T357	1		T359	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T63	1		T65	2		T236	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T63	4		T65	2		T236	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1		T65	1		T218	1		T250	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T354	1		T360	1		T361	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18992	1		T63	10		T64	92		T65	13
full_word	4426960	1		T1	265		T7	14865		T13	13

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	4445673	1		T1	265		T7	14865		T13	13
auto[TlIntgErrCmd]	85	1		T63	1		T65	5		T236	1
auto[TlIntgErrData]	99	1		T63	5		T65	7		T236	4
auto[TlIntgErrBoth]	95	1		T63	4		T65	4		T236	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	4422443	1		T1	265		T7	14865		T13	13
auto[1]	23509	1		T63	7		T64	110		T65	7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1287	1		T64	6		T197	5		T198	5
auto[TlIntgErrNone]	partial	auto[1]	17450	1		T64	86		T197	27		T198	114
auto[TlIntgErrNone]	full_word	auto[0]	4421042	1		T1	265		T7	14865		T13	13
auto[TlIntgErrNone]	full_word	auto[1]	5894	1		T64	24		T197	11		T198	39
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T65	4		T218	1		T219	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T63	1		T65	1		T236	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T360	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T357	1		T361	1		-	-
auto[TlIntgErrData]	partial	auto[0]	46	1		T63	2		T65	3		T236	4
auto[TlIntgErrData]	partial	auto[1]	43	1		T63	3		T65	2		T218	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T356	1		T362	1		T359	1
auto[TlIntgErrData]	full_word	auto[1]	6	1		T65	2		T355	1		T354	2
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T63	1		T65	2		T236	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T63	3		T65	1		T236	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T359	1		T360	1		T363	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1		T65	1		T250	1		T354	2