Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T8
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1658862024	1655496464	0	0
CheckNGreaterZero_A	4244	4244	0	0
GntImpliesReady_A	1658862024	461708732	0	0
GntImpliesValid_A	1658862024	461708732	0	0
GrantKnown_A	1658862024	1655496464	0	0
IdxKnown_A	1658862024	1655496464	0	0
IndexIsCorrect_A	1658862024	461708732	0	0
NoReadyValidNoGrant_A	1658862024	180642398	0	0
Priority_A	1658862024	485975142	0	0
ReadyAndValidImplyGrant_A	1658862024	461708732	0	0
ReqAndReadyImplyGrant_A	1658862024	461708732	0	0
ReqImpliesValid_A	1658862024	485975142	0	0
ValidKnown_A	1658862024	1655496464	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	1655496464	0	0
T1	132472	132120	0	0
T2	14356	11772	0	0
T3	4796	4480	0	0
T4	565760	565732	0	0
T5	964644	964400	0	0
T6	9232	8952	0	0
T7	192296	191932	0	0
T12	14136	11324	0	0
T20	9352	9016	0	0
T21	5364	5008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4244	4244	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T5	4	4	0	0
T6	4	4	0	0
T7	4	4	0	0
T12	4	4	0	0
T20	4	4	0	0
T21	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	461708732	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	40828	0	0
T8	0	29354	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	24964	0	0
T40	0	132722	0	0
T42	0	196198	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	461708732	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	40828	0	0
T8	0	29354	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	24964	0	0
T40	0	132722	0	0
T42	0	196198	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	1655496464	0	0
T1	132472	132120	0	0
T2	14356	11772	0	0
T3	4796	4480	0	0
T4	565760	565732	0	0
T5	964644	964400	0	0
T6	9232	8952	0	0
T7	192296	191932	0	0
T12	14136	11324	0	0
T20	9352	9016	0	0
T21	5364	5008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	1655496464	0	0
T1	132472	132120	0	0
T2	14356	11772	0	0
T3	4796	4480	0	0
T4	565760	565732	0	0
T5	964644	964400	0	0
T6	9232	8952	0	0
T7	192296	191932	0	0
T12	14136	11324	0	0
T20	9352	9016	0	0
T21	5364	5008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	461708732	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	40828	0	0
T8	0	29354	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	24964	0	0
T40	0	132722	0	0
T42	0	196198	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	180642398	0	0
T1	132472	2444	0	0
T2	14356	1130	0	0
T3	4796	256	0	0
T4	565760	16350	0	0
T5	964644	2960	0	0
T6	9232	316	0	0
T7	192296	65750	0	0
T8	0	963106	0	0
T12	14136	1536	0	0
T13	0	68	0	0
T20	9352	986	0	0
T21	5364	256	0	0
T22	0	876	0	0
T28	0	69276	0	0
T40	0	508	0	0
T42	0	103792	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	485975142	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	50212	0	0
T8	0	314314	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	28228	0	0
T40	0	132812	0	0
T42	0	257706	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	461708732	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	40828	0	0
T8	0	29354	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	24964	0	0
T40	0	132722	0	0
T42	0	196198	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	461708732	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	40828	0	0
T8	0	29354	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	24964	0	0
T40	0	132722	0	0
T42	0	196198	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	485975142	0	0
T1	132472	1502	0	0
T2	14356	308	0	0
T3	4796	64	0	0
T4	565760	2001730	0	0
T5	964644	465018	0	0
T6	9232	1124	0	0
T7	192296	50212	0	0
T8	0	314314	0	0
T12	14136	432	0	0
T13	0	26	0	0
T20	9352	356	0	0
T21	5364	64	0	0
T27	0	364080	0	0
T28	0	28228	0	0
T40	0	132812	0	0
T42	0	257706	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1658862024	1655496464	0	0
T1	132472	132120	0	0
T2	14356	11772	0	0
T3	4796	4480	0	0
T4	565760	565732	0	0
T5	964644	964400	0	0
T6	9232	8952	0	0
T7	192296	191932	0	0
T12	14136	11324	0	0
T20	9352	9016	0	0
T21	5364	5008	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T28
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414715506	413874116	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	414715506	127635105	0	0
GntImpliesValid_A	414715506	127635105	0	0
GrantKnown_A	414715506	413874116	0	0
IdxKnown_A	414715506	413874116	0	0
IndexIsCorrect_A	414715506	127635105	0	0
NoReadyValidNoGrant_A	414715506	47278812	0	0
Priority_A	414715506	133809718	0	0
ReadyAndValidImplyGrant_A	414715506	127635105	0	0
ReqAndReadyImplyGrant_A	414715506	127635105	0	0
ReqImpliesValid_A	414715506	133809718	0	0
ValidKnown_A	414715506	413874116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635105	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635105	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635105	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	47278812	0	0
T1	33118	674	0	0
T2	3589	565	0	0
T3	1199	128	0	0
T4	141440	2586	0	0
T5	241161	774	0	0
T6	2308	158	0	0
T7	48074	19283	0	0
T12	3534	768	0	0
T20	2338	493	0	0
T21	1341	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	133809718	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	12818	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635105	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635105	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	133809718	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	12818	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T8
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T8

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T28
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T8

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414715506	413874116	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	414715506	127635042	0	0
GntImpliesValid_A	414715506	127635042	0	0
GrantKnown_A	414715506	413874116	0	0
IdxKnown_A	414715506	413874116	0	0
IndexIsCorrect_A	414715506	127635042	0	0
NoReadyValidNoGrant_A	414715506	47278812	0	0
Priority_A	414715506	133809655	0	0
ReadyAndValidImplyGrant_A	414715506	127635042	0	0
ReqAndReadyImplyGrant_A	414715506	127635042	0	0
ReqImpliesValid_A	414715506	133809655	0	0
ValidKnown_A	414715506	413874116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635042	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635042	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635042	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	47278812	0	0
T1	33118	674	0	0
T2	3589	565	0	0
T3	1199	128	0	0
T4	141440	2586	0	0
T5	241161	774	0	0
T6	2308	158	0	0
T7	48074	19283	0	0
T12	3534	768	0	0
T20	2338	493	0	0
T21	1341	128	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	133809655	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	12818	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635042	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	127635042	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	10613	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	133809655	0	0
T1	33118	392	0	0
T2	3589	154	0	0
T3	1199	32	0	0
T4	141440	458470	0	0
T5	241161	83408	0	0
T6	2308	562	0	0
T7	48074	12818	0	0
T12	3534	216	0	0
T20	2338	178	0	0
T21	1341	32	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T7,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T7,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T8
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414715506	413874116	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	414715506	103219262	0	0
GntImpliesValid_A	414715506	103219262	0	0
GrantKnown_A	414715506	413874116	0	0
IdxKnown_A	414715506	413874116	0	0
IndexIsCorrect_A	414715506	103219262	0	0
NoReadyValidNoGrant_A	414715506	43042400	0	0
Priority_A	414715506	109177841	0	0
ReadyAndValidImplyGrant_A	414715506	103219262	0	0
ReqAndReadyImplyGrant_A	414715506	103219262	0	0
ReqImpliesValid_A	414715506	109177841	0	0
ValidKnown_A	414715506	413874116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219262	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219262	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219262	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	43042400	0	0
T1	33118	548	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	5589	0	0
T5	241161	706	0	0
T6	2308	0	0	0
T7	48074	13592	0	0
T8	0	481553	0	0
T12	3534	0	0	0
T13	0	34	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	438	0	0
T28	0	34638	0	0
T40	0	254	0	0
T42	0	51896	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	109177841	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	12288	0	0
T8	0	157157	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	14114	0	0
T40	0	66406	0	0
T42	0	128853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219262	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219262	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	109177841	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	12288	0	0
T8	0	157157	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	14114	0	0
T40	0	66406	0	0
T42	0	128853	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	0	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
124	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T7,T13

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T7,T13
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T8
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T7,T13

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T13
1	1	Covered	T1,T4,T5

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T13,T8
1	1	Covered	T1,T4,T5

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T7,T13

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	414715506	413874116	0	0
CheckNGreaterZero_A	1061	1061	0	0
GntImpliesReady_A	414715506	103219323	0	0
GntImpliesValid_A	414715506	103219323	0	0
GrantKnown_A	414715506	413874116	0	0
IdxKnown_A	414715506	413874116	0	0
IndexIsCorrect_A	414715506	103219323	0	0
NoReadyValidNoGrant_A	414715506	43042374	0	0
Priority_A	414715506	109177928	0	0
ReadyAndValidImplyGrant_A	414715506	103219323	0	0
ReqAndReadyImplyGrant_A	414715506	103219323	0	0
ReqImpliesValid_A	414715506	109177928	0	0
ValidKnown_A	414715506	413874116	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219323	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219323	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219323	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	43042374	0	0
T1	33118	548	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	5589	0	0
T5	241161	706	0	0
T6	2308	0	0	0
T7	48074	13592	0	0
T8	0	481553	0	0
T12	3534	0	0	0
T13	0	34	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	438	0	0
T28	0	34638	0	0
T40	0	254	0	0
T42	0	51896	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	109177928	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	12288	0	0
T8	0	157157	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	14114	0	0
T40	0	66406	0	0
T42	0	128853	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219323	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	103219323	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	9801	0	0
T8	0	14677	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	12482	0	0
T40	0	66361	0	0
T42	0	98099	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	109177928	0	0
T1	33118	359	0	0
T2	3589	0	0	0
T3	1199	0	0	0
T4	141440	542395	0	0
T5	241161	149101	0	0
T6	2308	0	0	0
T7	48074	12288	0	0
T8	0	157157	0	0
T12	3534	0	0	0
T13	0	13	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T27	0	182040	0	0
T28	0	14114	0	0
T40	0	66406	0	0
T42	0	128853	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0