Module Definition
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Module Instance : tb.dut.u_flash_mp.u_sw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.84 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_mp.u_hw_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.46 100.00 97.84 100.00 100.00 u_flash_mp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.u_region_sel

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.56 97.67 86.00 100.00 u_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=9 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_sw_sel

SCORELINE
100.00 100.00
tb.dut.u_eflash.u_region_sel

Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Line Coverage for Module : flash_mp_data_region_sel ( parameter Regions=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_flash_mp.u_hw_sel

Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Module : flash_mp_data_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T162,T86
11CoveredT4,T28,T33

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T116,T213
11CoveredT7,T28,T27

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT51,T86,T116
11CoveredT4,T33,T31

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T51,T208
11CoveredT4,T5,T28

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T33,T30
11CoveredT5,T7,T27

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T43,T51
11CoveredT5,T28,T27

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T47,T76
11CoveredT4,T28,T27

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT1,T4,T5

Branch Coverage for Module : flash_mp_data_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T2,T4
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T162,T86
11CoveredT4,T28,T33

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT86,T116,T213
11CoveredT7,T27,T33

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT51,T86,T116
11CoveredT4,T33,T31

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T51,T208
11CoveredT4,T5,T28

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T33,T30
11CoveredT5,T27,T33

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T43,T51
11CoveredT5,T28,T27

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T76,T264
11CoveredT4,T28,T27

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T5,T7
11CoveredT1,T4,T5

Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
TOTAL88100.00
CONT_ASSIGN2811100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T2,T12,T16
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
CONT_ASSIGN3011100.00
ALWAYS3500
ALWAYS3533100.00
ALWAYS4944100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
30 8 8
35 1 1
36 1 1
39 1 1
49 1 1
50 1 1
51 1 1
52 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
TotalCoveredPercent
Conditions2424100.00
Logical2424100.00
Non-Logical00
Event00

 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT213,T265,T266
11CoveredT161,T36,T264

 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT267,T265,T268
11CoveredT28,T24,T47

 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT213,T269,T270
11CoveredT161,T182,T36

 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT213,T265,T271
11CoveredT30,T264,T162

 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT272,T273,T267
11CoveredT7,T24,T161

 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT105,T274,T275
11CoveredT29,T30,T161

 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T276,T213
11CoveredT24,T51,T105

 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T28,T24
11CoveredT1,T7,T13

Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 51 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 51 if (region_sel[i])

Branches:
-1-StatusTests
1 Covered T1,T7,T13
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%