Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.87	100.00	91.51		100.00	97.83	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.91	100.00	98.46	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.55	100.00	84.91		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T108,T9
1	0	Covered	T135,T108,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T135,T108,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10,T23
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T108,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T22,T41

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T22,T41
1	1	Covered	T27,T22,T41

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T22,T41
1	1	Covered	T27,T22,T41

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T27,T22,T41
StCalcMask	237	Covered	T27,T22,T41
StCalcPlainEcc	215	Covered	T4,T5,T6
StDisabled	193	Covered	T2,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T6
StPostPack	218	Covered	T4,T5,T42
StPrePack	195	Covered	T4,T5,T42
StReqFlash	237	Covered	T4,T5,T6
StScrambleData	244	Covered	T27,T22,T41
StWaitFlash	270	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T27,T22,T41
StCalcMask->StScrambleData	244	Covered	T27,T22,T41
StCalcPlainEcc->StCalcMask	237	Covered	T27,T22,T41
StCalcPlainEcc->StReqFlash	237	Covered	T4,T5,T6
StIdle->StDisabled	193	Covered	T2,T12,T13
StIdle->StPackData	197	Covered	T4,T5,T6
StIdle->StPrePack	195	Covered	T4,T5,T42
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T6
StPackData->StPostPack	218	Covered	T4,T5,T42
StPostPack->StCalcPlainEcc	231	Covered	T4,T5,T42
StPrePack->StPackData	205	Covered	T4,T5,T42
StReqFlash->StIdle	273	Covered	T4,T5,T6
StReqFlash->StWaitFlash	270	Covered	T4,T5,T6
StScrambleData->StCalcEcc	252	Covered	T27,T22,T41
StWaitFlash->StIdle	280	Covered	T4,T5,T6

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14,T15
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T22,T41
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T27,T22,T41
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T27,T22,T41
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T22,T41
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T27,T22,T41
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T22,T41
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T6
0	0	1	-	-	Covered	T27,T22,T41
0	0	0	1	-	Covered	T27,T22,T41
0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	829431012	2404547	0	0
PostPackRule_A	829431012	30098	0	0
PrePackRule_A	829431012	14987	0	0
WidthCheck_A	2122	2122	0	0
u_state_regs_A	829431012	827748232	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	829431012	2404547	0	0
T4	282880	245	0	0
T5	482322	77	0	0
T6	4616	1	0	0
T7	96148	0	0	0
T12	7068	0	0	0
T13	1686	0	0	0
T16	7200	0	0	0
T20	4676	0	0	0
T21	2682	0	0	0
T22	0	4	0	0
T25	0	3	0	0
T27	0	1122	0	0
T31	0	394	0	0
T33	0	336	0	0
T34	0	64	0	0
T40	0	4	0	0
T41	0	65942	0	0
T42	0	1194	0	0
T56	1966	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	829431012	30098	0	0
T4	282880	13	0	0
T5	482322	48	0	0
T6	4616	0	0	0
T7	96148	0	0	0
T12	7068	0	0	0
T13	1686	0	0	0
T16	7200	0	0	0
T20	4676	0	0	0
T21	2682	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T30	0	1	0	0
T33	0	9	0	0
T40	0	2	0	0
T41	0	11	0	0
T42	0	586	0	0
T56	1966	0	0	0
T95	0	53	0	0
T153	0	1	0	0
T185	0	5	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	829431012	14987	0	0
T4	282880	8	0	0
T5	482322	22	0	0
T6	4616	0	0	0
T7	96148	0	0	0
T12	7068	0	0	0
T13	1686	0	0	0
T16	7200	0	0	0
T20	4676	0	0	0
T21	2682	0	0	0
T29	0	1	0	0
T30	0	1	0	0
T33	0	8	0	0
T40	0	3	0	0
T41	0	15	0	0
T42	0	201	0	0
T44	0	1	0	0
T56	1966	0	0	0
T95	0	21	0	0
T112	0	14	0	0
T185	0	5	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2122	2122	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T12	2	2	0	0
T20	2	2	0	0
T21	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	829431012	827748232	0	0
T1	66236	66060	0	0
T2	7178	5886	0	0
T3	2398	2240	0	0
T4	282880	282866	0	0
T5	482322	482200	0	0
T6	4616	4476	0	0
T7	96148	95966	0	0
T12	7068	5662	0	0
T20	4676	4508	0	0
T21	2682	2504	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T108,T9
1	0	Covered	T135,T108,T9

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T135,T108,T9

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T23
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T135,T108,T9
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T42

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T42

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T27,T22,T41

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T22,T41
1	1	Covered	T27,T22,T41

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T22,T41
1	1	Covered	T27,T22,T41

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T6
1	1	0	Covered	T4,T5,T6
1	1	1	Covered	T4,T5,T6

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T27,T22,T41
StCalcMask	237	Covered	T27,T22,T41
StCalcPlainEcc	215	Covered	T4,T5,T6
StDisabled	193	Covered	T2,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T6
StPostPack	218	Covered	T4,T5,T42
StPrePack	195	Covered	T4,T5,T42
StReqFlash	237	Covered	T4,T5,T6
StScrambleData	244	Covered	T27,T22,T41
StWaitFlash	270	Covered	T4,T5,T6

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T27,T22,T41
StCalcMask->StScrambleData	244	Covered	T27,T22,T41
StCalcPlainEcc->StCalcMask	237	Covered	T27,T22,T41
StCalcPlainEcc->StReqFlash	237	Covered	T4,T5,T6
StIdle->StDisabled	193	Covered	T2,T12,T13
StIdle->StPackData	197	Covered	T4,T5,T6
StIdle->StPrePack	195	Covered	T4,T5,T42
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T6
StPackData->StPostPack	218	Covered	T4,T5,T42
StPostPack->StCalcPlainEcc	231	Covered	T4,T5,T42
StPrePack->StPackData	205	Covered	T4,T5,T42
StReqFlash->StIdle	273	Covered	T4,T5,T6
StReqFlash->StWaitFlash	270	Covered	T4,T5,T6
StScrambleData->StCalcEcc	252	Covered	T27,T22,T41
StWaitFlash->StIdle	280	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T6
0	0	1	Covered	T4,T5,T6
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14,T15
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T22,T41
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T6
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T27,T22,T41
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T27,T22,T41
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T22,T41
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T27,T22,T41
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T22,T41
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T6
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T6
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T6
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T6
0	0	1	-	-	Covered	T27,T22,T41
0	0	0	1	-	Covered	T27,T22,T41
0	0	0	0	1	Covered	T4,T5,T6
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T6
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	414715506	1227167	0	0
PostPackRule_A	414715506	17509	0	0
PrePackRule_A	414715506	9005	0	0
WidthCheck_A	1061	1061	0	0
u_state_regs_A	414715506	413874116	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	1227167	0	0
T4	141440	202	0	0
T5	241161	36	0	0
T6	2308	1	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	1	0	0
T27	0	712	0	0
T33	0	104	0	0
T34	0	64	0	0
T40	0	2	0	0
T41	0	33161	0	0
T42	0	674	0	0
T56	983	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	17509	0	0
T4	141440	6	0	0
T5	241161	24	0	0
T6	2308	0	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T30	0	1	0	0
T33	0	6	0	0
T40	0	1	0	0
T41	0	6	0	0
T42	0	279	0	0
T56	983	0	0	0
T95	0	21	0	0
T153	0	1	0	0
T185	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	9005	0	0
T4	141440	3	0	0
T5	241161	7	0	0
T6	2308	0	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T30	0	1	0	0
T33	0	6	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	112	0	0
T44	0	1	0	0
T56	983	0	0	0
T95	0	9	0	0
T185	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	1	1
122	1	1
126	1	1
130	1	1
131	1	1
133	1	1
138	1	1
143	1	1
144	1	1
147	1	1
148	1	1
151	1	1
152	1	1
153	1	1
155	1	1
156	1	1
158	1	1
			MISSING_ELSE
164	3	3
174	1	1
176	1	1
177	1	1
178	1	1
179	1	1
180	1	1
181	1	1
182	1	1
183	1	1
184	1	1
186	1	1
189	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
			MISSING_ELSE
203	1	1
204	1	1
205	1	1
			MISSING_ELSE
210	1	1
211	1	1
213	1	1
215	1	1
216	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	1	1
227	1	1
230	1	1
231	1	1
			MISSING_ELSE
236	1	1
237	1	1
241	1	1
243	1	1
244	1	1
			MISSING_ELSE
249	1	1
251	1	1
252	1	1
			MISSING_ELSE
257	1	1
262	1	1
263	1	1
269	1	1
270	1	1
272	1	1
273	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
285	1	1
299	1	1
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
			MISSING_ELSE
314	1	1
323	1	1
324	1	1
325	1	1
326	1	1
			MISSING_ELSE
331	1	1
352	1	1
355	1	1
365	1	1
366	1	1
369	1	1
370	1	1
372	1	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T42

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T42

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10
1	0	Covered	T9,T10

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T42
1	1	Covered	T9,T10

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T9,T10
1	0	Covered	T1,T4,T5

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T42

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T42
1	Covered	T4,T5,T42

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T42
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T42

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T42
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T4,T5,T42
1	Covered	T4,T5,T42

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T42
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T14,T15
1	Covered	T4,T5,T42

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T42
1	Covered	T27,T41,T25

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T42
1	Covered	T4,T5,T42

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T4,T5,T42
1	Covered	T4,T5,T42

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T42
1	1	Covered	T4,T5,T42

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T13,T28,T22
1	0	Covered	T27,T41,T25
1	1	Covered	T27,T41,T25

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T13,T28,T22
1	0	Covered	T27,T41,T25
1	1	Covered	T27,T41,T25

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T4,T5,T42
1	1	0	Covered	T4,T5,T42
1	1	1	Covered	T4,T5,T42

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T42

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T27,T25,T31
StCalcMask	237	Covered	T27,T25,T31
StCalcPlainEcc	215	Covered	T4,T5,T42
StDisabled	193	Covered	T2,T12,T13
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T4,T5,T42
StPostPack	218	Covered	T4,T5,T42
StPrePack	195	Covered	T4,T5,T42
StReqFlash	237	Covered	T4,T5,T42
StScrambleData	244	Covered	T27,T25,T31
StWaitFlash	270	Covered	T4,T5,T42

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T27,T25,T31
StCalcMask->StScrambleData	244	Covered	T27,T25,T31
StCalcPlainEcc->StCalcMask	237	Covered	T27,T25,T31
StCalcPlainEcc->StReqFlash	237	Covered	T4,T5,T42
StIdle->StDisabled	193	Covered	T2,T12,T13
StIdle->StPackData	197	Covered	T4,T5,T42
StIdle->StPrePack	195	Covered	T4,T5,T42
StPackData->StCalcPlainEcc	215	Covered	T4,T5,T42
StPackData->StPostPack	218	Covered	T4,T5,T42
StPostPack->StCalcPlainEcc	231	Covered	T4,T5,T42
StPrePack->StPackData	205	Covered	T4,T5,T42
StReqFlash->StIdle	273	Covered	T4,T5,T42
StReqFlash->StWaitFlash	270	Covered	T4,T5,T42
StScrambleData->StCalcEcc	252	Covered	T27,T25,T31
StWaitFlash->StIdle	280	Covered	T4,T5,T42

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T42
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T42
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T42
0	1	Covered	T1,T4,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T4,T5,T42
0	0	1	Covered	T4,T5,T42
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T14,T15
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T4,T5,T42
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T14,T15
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T41,T25
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T4,T5,T42
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T27,T41,T25
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T27,T41,T25
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T27,T41,T25
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T27,T41,T25
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T41,T25
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T4,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T4,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T4,T5,T42
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T4,T5,T42
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T5,T42
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T4,T5,T42
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T4,T5,T42
0	0	1	-	-	Covered	T27,T41,T25
0	0	0	1	-	Covered	T27,T41,T25
0	0	0	0	1	Covered	T4,T5,T42
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T42
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	414715506	1177380	0	0
PostPackRule_A	414715506	12589	0	0
PrePackRule_A	414715506	5982	0	0
WidthCheck_A	1061	1061	0	0
u_state_regs_A	414715506	413874116	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	1177380	0	0
T4	141440	43	0	0
T5	241161	41	0	0
T6	2308	0	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	3	0	0
T25	0	3	0	0
T27	0	410	0	0
T31	0	394	0	0
T33	0	232	0	0
T40	0	2	0	0
T41	0	32781	0	0
T42	0	520	0	0
T56	983	0	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	12589	0	0
T4	141440	7	0	0
T5	241161	24	0	0
T6	2308	0	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T22	0	1	0	0
T25	0	1	0	0
T33	0	3	0	0
T40	0	1	0	0
T41	0	5	0	0
T42	0	307	0	0
T56	983	0	0	0
T95	0	32	0	0
T185	0	4	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	5982	0	0
T4	141440	5	0	0
T5	241161	15	0	0
T6	2308	0	0	0
T7	48074	0	0	0
T12	3534	0	0	0
T13	843	0	0	0
T16	3600	0	0	0
T20	2338	0	0	0
T21	1341	0	0	0
T29	0	1	0	0
T33	0	2	0	0
T40	0	1	0	0
T41	0	9	0	0
T42	0	89	0	0
T56	983	0	0	0
T95	0	12	0	0
T112	0	14	0	0
T185	0	4	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1061	1061	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414715506	413874116	0	0
T1	33118	33030	0	0
T2	3589	2943	0	0
T3	1199	1120	0	0
T4	141440	141433	0	0
T5	241161	241100	0	0
T6	2308	2238	0	0
T7	48074	47983	0	0
T12	3534	2831	0	0
T20	2338	2254	0	0
T21	1341	1252	0	0